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REJ09B0179-0122
16
M16C/30P Group
Hardware Manual
RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES
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Rev.1.22 Revision Date:Mar 29, 2007
www.renesas.com
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries.
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. The characteristics of MPU/MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different type numbers, implement a system-evaluation test for each of the products.
How to Use This Manual
1. Purpose and Target Readers
This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the MCU. It is intended for users designing application systems incorporating the MCU. A basic knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual. The manual comprises an overview of the product; descriptions of the CPU, system control functions, peripheral functions, and electrical characteristics; and usage notes. Particular attention should be paid to the precautionary notes when using the manual. These notes occur within the body of the text, at the end of each section, and in the Usage Notes section.
The revision history summarizes the locations of revisions and additions. It does not list all revisions. Refer to the text of the manual for details. The following documents apply to the M16C/30P Group. Make sure to refer to the latest versions of these documents. The newest versions of the documents listed may be obtained from the Renesas Technology Web site. Description Document Title Document No. Hardware overview and electrical characteristics M16C/30P Group REJ03B0088 Datasheet M16C/30P Group This hardware Hardware manual Hardware specifications (pin assignments, Hardware Manual manual memory maps, peripheral function specifications, electrical characteristics, timing charts) and operation description Note: Refer to the application notes for details on using peripheral functions. Available from Renesas Application note Information on using peripheral functions and Technology Web site. application examples Sample programs Information on writing programs in assembly language and C Renesas Product specifications, updates on documents, technical update etc. Document Type Datasheet
2.
Notation of Numbers and Symbols
The notation conventions for register names, bit names, numbers, and symbols used in this manual are described below. (1) Register Names, Bit Names, and Pin Names Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word "register," "bit," or "pin" to distinguish the three categories. Examples the PM03 bit in the PM0 register P3_5 pin, VCC pin Notation of Numbers The indication "b" is appended to numeric values given in binary format. However, nothing is appended to the values of single bits. The indication "h" is appended to numeric values given in hexadecimal format. Nothing is appended to numeric values given in decimal format. Examples Binary: 11b Hexadecimal: EFA0h Decimal: 1234
(2)
3.
Register Notation
The symbols and terms used in register diagrams are described below.
XXX Register
b7 b6 b5 b4 b3 b2 b1 b0
*1
Symbol XXX Address XXX After Reset 00h
0
*5
Bit Symbol
XXX0
Bit Name
XXX Bit
b1 b0
Function
1 0: XXX 0 1: XXX 1 0: Avoid this setting 1 1: XXX
RW RW
*2
XXX1
RW
(b2)
Nothing is assigned. When write, should set to "0". When read, its content is indeterminate.
*3
RW
(b3)
Reserved Bit
Must set to "0"
*4
XXX4
XXX Bit
Function varies depending on each operation mode
RW
XXX5
WO
XXX6 0: XXX 1: XXX
RW
XXX7
XXX Bit
RO
*1 Blank: Set to 0 or 1 according to the application. 0: Set to 0. 1: Set to 1. X: Nothing is assigned. *2 RW: Read and write. RO: Read only. WO: Write only. -: Nothing is assigned. *3 * Reserved bit Reserved bit. Set to specified value. *4 * Nothing is assigned Nothing is assigned to the bit. As the bit may be used for future functions, if necessary, set to 0. * Do not set to a value Operation is not guaranteed when a value is set. * Function varies according to the operating mode. The function of the bit varies with the peripheral function mode. Refer to the register diagram for information on the individual modes.
4.
List of Abbreviations and Acronyms
Abbreviation ACIA bps CRC DMA DMAC GSM Hi-Z IEBus I/O IrDA LSB MSB NC PLL PWM SFR SIM UART VCO Full Form Asynchronous Communication Interface Adapter bits per second Cyclic Redundancy Check Direct Memory Access Direct Memory Access Controller Global System for Mobile Communications High Impedance Inter Equipment bus Input/Output Infrared Data Association Least Significant Bit Most Significant Bit Non-Connection Phase Locked Loop Pulse Width Modulation Special Function Registers Subscriber Identity Module Universal Asynchronous Receiver/Transmitter Voltage Controlled Oscillator
All trademarks and registered trademarks are the property of their respective owners. IEBus is a registered trademark of NEC Electronics Corporation.
Table of Contents
SFR Page Reference ........................................................................................................................... B - 1 1. 1.1 1.2 1.3 1.4 1.5 1.6 2. Overview ......................................................................................................................................... 1 Applications ............................................................................................................................................... 1 Performance Outline .................................................................................................................................. 2 Block Diagram .......................................................................................................................................... 3 Product List ............................................................................................................................................... 4 Pin Configuration ...................................................................................................................................... 8 Pin Description ........................................................................................................................................ 12 Central Processing Unit (CPU) ..................................................................................................... 14 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.8.1 2.8.2 2.8.3 2.8.4 2.8.5 2.8.6 2.8.7 2.8.8 2.8.9 2.8.10 3. 4. 5. Data Registers (R0, R1, R2 and R3) ....................................................................................................... Address Registers (A0 and A1) ............................................................................................................... Frame Base Register (FB) ....................................................................................................................... Interrupt Table Register (INTB) .............................................................................................................. Program Counter (PC) ............................................................................................................................. User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) .................................................................. Static Base Register (SB) ........................................................................................................................ Flag Register (FLG) ................................................................................................................................ Carry Flag (C Flag) ............................................................................................................................. Debug Flag (D Flag) ........................................................................................................................... Zero Flag (Z Flag) ............................................................................................................................... Sign Flag (S Flag) ............................................................................................................................... Register Bank Select Flag (B Flag) .................................................................................................... Overflow Flag (O Flag) ...................................................................................................................... Interrupt Enable Flag (I Flag) ............................................................................................................. Stack Pointer Select Flag (U Flag) ..................................................................................................... Processor Interrupt Priority Level (IPL) ............................................................................................. Reserved Area ..................................................................................................................................... 14 15 15 15 15 15 15 15 15 15 15 15 15 15 15 16 16 16
Memory ......................................................................................................................................... 17 Special Function Register (SFR) .................................................................................................. 18 Reset ............................................................................................................................................ 23 5.1 5.1.1 5.1.2 5.2 5.3 5.4 Hardware Reset ....................................................................................................................................... Reset on a Stable Supply Voltage ....................................................................................................... Power-on Reset ................................................................................................................................... Software Reset ......................................................................................................................................... Internal Space .......................................................................................................................................... Cold Start-up / Warm Start-up Determine Function ............................................................................... 23 23 23 25 26 27
6. 6.1 6.2
Processor Mode ............................................................................................................................ 29 Types of Processor Mode ........................................................................................................................ 29 Setting Processor Modes ......................................................................................................................... 29
A-1
7.
Bus ................................................................................................................................................ 34 7.1 Bus Mode ................................................................................................................................................ 34 7.2 Bus Control .............................................................................................................................................. 34 7.2.1 Address Bus ........................................................................................................................................ 34 7.2.2 Data Bus .............................................................................................................................................. 34 7.2.3 Chip Select Signal ............................................................................................................................... 35 7.2.4 Read and Write Signals ....................................................................................................................... 37 7.2.5 ALE Signal ......................................................................................................................................... 37 7.2.6 RDY Signal ......................................................................................................................................... 38 7.2.7 HOLD Signal ...................................................................................................................................... 39 7.2.8 BCLK Output ...................................................................................................................................... 39 7.2.9 External Bus Status When Internal Area Accessed ........................................................................... 41 7.2.10 Software Wait ..................................................................................................................................... 41
8. 8.1 9.
Memory Space Expansion Function ............................................................................................. 43 1-Mbyte Mode ......................................................................................................................................... 43 Clock Generating Circuit ............................................................................................................... 45 9.1 9.1.1 9.1.2 9.2 9.2.1 9.2.2 9.3 9.4 9.4.1 9.4.2 9.4.3 Types of the Clock Generating Circuit .................................................................................................... Main Clock ......................................................................................................................................... Sub Clock ............................................................................................................................................ CPU Clock and Peripheral Function Clock ............................................................................................. CPU Clock and BCLK ........................................................................................................................ Peripheral Function Clock (f1, f2, f8, f32, f1SIO, f2SIO, f8SIO, f32SIO, fAD, fC32) ..................... Clock Output Function ............................................................................................................................ Power Control .......................................................................................................................................... Normal Operation Mode ..................................................................................................................... Wait Mode .......................................................................................................................................... Stop Mode ........................................................................................................................................... 45 49 50 51 51 51 51 52 52 53 55
10. 11.
Protection ...................................................................................................................................... 60 Interrupt ........................................................................................................................................ 61 Type of Interrupts .................................................................................................................................... Software Interrupts .................................................................................................................................. Undefined Instruction Interrupt .......................................................................................................... Overflow Interrupt .............................................................................................................................. BRK Interrupt ..................................................................................................................................... INT Instruction Interrupt .................................................................................................................... Hardware Interrupts ................................................................................................................................. Special Interrupts ................................................................................................................................ Peripheral Function Interrupts ............................................................................................................ Interrupts and Interrupt Vector ................................................................................................................ Fixed Vector Tables ............................................................................................................................ Relocatable Vector Tables .................................................................................................................. 61 62 62 62 62 62 63 63 63 64 64 65
11.1 11.2 11.2.1 11.2.2 11.2.3 11.2.4 11.3 11.3.1 11.3.2 11.4 11.4.1 11.4.2
A-2
11.5 Interrupt Control ...................................................................................................................................... 11.5.1 I Flag ................................................................................................................................................... 11.5.2 IR Bit ................................................................................................................................................... 11.5.3 ILVL2 to ILVL0 Bits and IPL ............................................................................................................ 11.5.4 Interrupt Sequence .............................................................................................................................. 11.5.5 Interrupt Response Time ..................................................................................................................... 11.5.6 Variation of IPL when Interrupt Request is Accepted ........................................................................ 11.5.7 Saving Registers ................................................................................................................................. 11.5.8 Returning from an Interrupt Routine .................................................................................................. 11.5.9 Interrupt Priority ................................................................................................................................. 11.5.10 Interrupt Priority Resolution Circuit ................................................................................................... 11.6 INT Interrupt ............................................................................................................................................ 11.7 NMI Interrupt ........................................................................................................................................... 11.8 Key Input Interrupt .................................................................................................................................. 11.9 Address Match Interrupt .......................................................................................................................... 12. 13.
66 68 68 68 69 70 70 71 73 73 74 75 76 76 77
Watchdog Timer ............................................................................................................................ 79 DMAC ........................................................................................................................................... 81 Transfer Cycles ........................................................................................................................................ Effect of Source and Destination Addresses ....................................................................................... Effect of BYTE Pin Level .................................................................................................................. Effect of Software Wait ...................................................................................................................... Effect of RDY Signal .......................................................................................................................... DMA Transfer Cycles ............................................................................................................................. DMA Enable ............................................................................................................................................ DMA Request .......................................................................................................................................... Channel Priority and DMA Transfer Timing .......................................................................................... 87 87 87 87 87 89 90 90 91
13.1 13.1.1 13.1.2 13.1.3 13.1.4 13.2 13.3 13.4 13.5 14.
Timers ........................................................................................................................................... 92
14.1 Timer A ................................................................................................................................................... 94 14.1.1 Timer Mode ........................................................................................................................................ 99 14.1.2 Event Counter Mode ......................................................................................................................... 101 14.1.3 One-shot Timer Mode ....................................................................................................................... 105 14.1.4 Pulse Width Modulation (PWM) Mode ............................................................................................ 107 14.2 Timer B .................................................................................................................................................. 110 14.2.1 Timer Mode ...................................................................................................................................... 113 14.2.2 Event Counter Mode ......................................................................................................................... 114 14.2.3 Pulse Period and Pulse Width Measurement Mode .......................................................................... 116 15. Serial Interface ............................................................................................................................. 119
15.1 UARTi (i=0 to 2) ................................................................................................................................... 119 15.1.1 Clock Synchronous Serial I/O Mode ................................................................................................ 130 15.1.2 Clock Asynchronous Serial I/O (UART) Mode ............................................................................... 138 15.1.3 Special Mode 1 (I2C mode) .............................................................................................................. 146 15.1.4 Special Mode 2 ................................................................................................................................. 156 15.1.5 Special Mode 3 (IE mode)(UART2) ................................................................................................ 161 15.1.6 Special Mode 4 (SIM Mode) (UART2) ............................................................................................ 163
A-3
16.
A/D Converter ............................................................................................................................. 168 172 172 175 178 178 178 178 178 179
16.1 Mode Description .................................................................................................................................. 16.1.1 One-Shot Mode ................................................................................................................................. 16.1.2 Repeat Mode ..................................................................................................................................... 16.2 Function ................................................................................................................................................. 16.2.1 Resolution Select Function ............................................................................................................... 16.2.2 Sample and Hold ............................................................................................................................... 16.2.3 Extended Analog Input Pins ............................................................................................................. 16.2.4 Current Consumption Reducing Function ........................................................................................ 16.2.5 Output Impedance of Sensor under A/D Conversion ....................................................................... 17. 18. 18.1 18.2 18.3 18.4 19.
CRC Calculation ......................................................................................................................... 180 Programmable I/O Ports ............................................................................................................. 182 Port Pi Direction Register (PDi Register, i = 0 to 10) ........................................................................... Port Pi Register (Pi Register, i = 0 to 10) .............................................................................................. Pull-up Control Register 0 to Pull-up Control Register 2 (PUR0 to PUR2 Registers) ......................... Port Control Register (PCR Register) ................................................................................................... 182 182 182 182
Flash Memory Version ................................................................................................................ 195 Memory Map ......................................................................................................................................... Boot Mode ........................................................................................................................................ Functions To Prevent Flash Memory from Rewriting .......................................................................... ROM Code Protect Function ............................................................................................................ ID Code Check Function .................................................................................................................. Forced Erase Function ...................................................................................................................... CPU Rewrite Mode ............................................................................................................................... EW0 Mode ........................................................................................................................................ EW1 Mode ........................................................................................................................................ Flash Memory Control Register (FMR0 and FMR1 registers) ......................................................... Precautions on CPU Rewrite Mode .................................................................................................. Software Commands ........................................................................................................................ Data Protect Function ....................................................................................................................... Status Register .................................................................................................................................. Full Status Check .............................................................................................................................. Standard Serial I/O Mode ...................................................................................................................... ID Code Check Function .................................................................................................................. Example of Circuit Application in the Standard Serial I/O Mode .................................................... Parallel I/O Mode .................................................................................................................................. User ROM and Boot ROM Areas ..................................................................................................... ROM Code Protect Function ............................................................................................................ 196 197 197 197 198 199 201 202 202 202 210 212 217 217 219 221 221 225 227 227 227
19.1 19.1.1 19.2 19.2.1 19.2.2 19.2.3 19.3 19.3.1 19.3.2 19.3.3 19.3.4 19.3.5 19.3.6 19.3.7 19.3.8 19.4 19.4.1 19.4.2 19.5 19.5.1 19.5.2 20.
One Time Flash Version ............................................................................................................. 228 229 231 231 231
20.1 Low Consumption Mode ....................................................................................................................... 20.2 Functions to Prevent One Time Flash Version from Being Read ......................................................... 20.2.1 ROM Code Protect Function ............................................................................................................ 20.2.2 ID Code Check Function ..................................................................................................................
A-4
20.3 Standard Serial I/O Mode ...................................................................................................................... 232 20.3.1 ID Code Check Function .................................................................................................................. 232 20.3.2 Example of Circuit Application in the Standard Serial I/O Mode .................................................... 235 21. 22. Electrical Characteristics ............................................................................................................ 237 Usage Precaution ....................................................................................................................... 267 267 267 268 269 270 271 272 272 272 272 273 273 274 274 275 275 276 276 278 279 279 280 281 283 283 283 284 284 284 284 284 284 284 284 285 285 285 285 285 285
22.1 SFR ........................................................................................................................................................ 22.1.1 Register Settings ............................................................................................................................... 22.2 Reset ...................................................................................................................................................... 22.3 Bus ......................................................................................................................................................... 22.4 Precautions for Power Control .............................................................................................................. 22.5 Precautions for Protect .......................................................................................................................... 22.6 Precautions for Interrupt ........................................................................................................................ 22.6.1 Reading address 00000h ................................................................................................................... 22.6.2 Setting the SP .................................................................................................................................... 22.6.3 The NMI Interrupt ............................................................................................................................. 22.6.4 Changing the Interrupt Generate Factor ........................................................................................... 22.6.5 INT Interrupt ..................................................................................................................................... 22.6.6 Rewrite the Interrupt Control Register ............................................................................................. 22.6.7 Watchdog Timer Interrupt ................................................................................................................ 22.7 Precautions for DMAC .......................................................................................................................... 22.7.1 Write to DMAE Bit in DMiCON Register ....................................................................................... 22.8 Precautions for Timers .......................................................................................................................... 22.8.1 Timer A ............................................................................................................................................. 22.8.2 Timer B ............................................................................................................................................. 22.9 Precautions for Serial interface ............................................................................................................. 22.9.1 Clock Synchronous Serial I/O .......................................................................................................... 22.9.2 UART ................................................................................................................................................ 22.10 A/D Converter ....................................................................................................................................... 22.11 Precautions for Programmable I/O Ports ............................................................................................... 22.12 Electric Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers 22.13 Mask ROM ............................................................................................................................................ 22.14 Flash Memory Version .......................................................................................................................... 22.14.1 Functions to Inhibit Rewriting Flash Memory Rewrite .................................................................... 22.14.2 Stop mode ......................................................................................................................................... 22.14.3 Wait mode ......................................................................................................................................... 22.14.4 Low power dissipation mode ............................................................................................................ 22.14.5 Writing command and data ............................................................................................................... 22.14.6 Program Command ........................................................................................................................... 22.14.7 Lock Bit Program Command ............................................................................................................ 22.14.8 Operation speed ................................................................................................................................ 22.14.9 Prohibited instructions ...................................................................................................................... 22.14.10 Interrupts ........................................................................................................................................... 22.14.11 How to access ................................................................................................................................... 22.14.12 Writing in the user ROM area ........................................................................................................... 22.14.13 DMA transfer ....................................................................................................................................
A-5
22.15 One Time Flash Version ........................................................................................................................ 22.15.1 Stop mode ......................................................................................................................................... 22.15.2 Wait mode ......................................................................................................................................... 22.15.3 Operation speed ................................................................................................................................ 22.15.4 Prohibited Instructions ...................................................................................................................... 22.15.5 Interrupts ........................................................................................................................................... 22.15.6 How to access ................................................................................................................................... 22.16 Precautions for Noise ............................................................................................................................
286 286 286 286 286 286 286 287
Appendix 1. Package Dimensions ........................................................................................................ 288 Appendix 2. Difference between M16C/62P and M16C/30P ................................................................ 289 Register Index ........................................................................................................................................ 291
A-6
SFR Page Reference
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh Register Symbol Page Address 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h to 01B3h 01B4h 01B5h 01B6h 01B7h DMA0 Transfer Counter TCR0 86 01B8h to 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025Ah 025Bh 025Ch 025Dh 025Eh 025Fh 0260h to 0335h 0336h 0337h 0338h 0339h 033Ah 033Bh 033Ch 033Dh 033Eh 033Fh Register Symbol Page
Processor Mode Register 0 Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 Chip Select Control Register Address Match Interrupt Enable Register Protect Register
PM0 PM1 CM0 CM1 CSR AIER PRCR
30 31 47 48 35 78 60
INT3 Interrupt Control Register UART1 BUS Collision Detection Interrupt Control Register UART0 BUS Collision Detection Interrupt Control Register INT4 Interrupt Control Register UART2 Bus Collision Detection Interrupt Control Register DMA0 Interrupt Control Register DMA1 Interrupt Control Register Key Input Interrupt Control Register A/D Conversion Interrupt Control Register UART2 Transmit Interrupt Control Register UART2 Receive Interrupt Control Register UART0 Transmit Interrupt Control Register UART0 Receive Interrupt Control Register UART1 Transmit Interrupt Control Register UART1 Receive Interrupt Control Register Timer A0 Interrupt Control Register Timer A1 Interrupt Control Register Timer A2 Interrupt Control Register
INT3IC U1BCNIC U0BCNIC INT4IC BCNIC DM0IC DM1IC KUPIC ADIC S2TIC S2RIC S0TIC S0RIC S1TIC S1RIC TA0IC TA1IC TA2IC
67 66 66 67 66 66 66 66 66 66 66 66 66 66 66 66 66 66
Watchdog Timer Start Register Watchdog Timer Control Register Address Match Interrupt Register 0
WDTS WDC RMAD0
80 28, 80 78
Address Match Interrupt Register 1
RMAD1
78
Timer B0 Interrupt Control Register Timer B1 Interrupt Control Register Timer B2 Interrupt Control Register INT0 Interrupt Control Register INT1 Interrupt Control Register INT2 Interrupt Control Register
TB0IC TB1IC TB2IC INT0IC INT1IC INT2IC
66 66 66 67 67 67
DMA0 Source Pointer
SAR0
86
DMA0 Destination Pointer
DAR0
86
Flash Memory Control Register 1(2) Flash Memory Control Register 0(2)
FMR1 FMR0
204 203
DMA0 Control Register
DM0CON
85
DMA1 Source Pointer
SAR1
86
DMA1 Destination Pointer
DAR1
86
Peripheral Clock Select Register
PCLKR
48
DMA1 Transfer Counter
TCR1
86
DMA1 Control Register
DM1CON
85
NOTES: 1. Blank columns are all reserved space. No access is allowed. 2. This register is included in the flash memory version. 3. This register is included in the One time flash version.
B-1
Address 0340h 0341h 0342h 0343h 0344h 0345h 0346h 0347h 0348h 0349h 034Ah 034Bh 034Ch 034Dh 034Eh 034Fh 0350h 0351h 0352h 0353h 0354h 0355h 0356h 0357h 0358h 0359h 035Ah 035Bh 035Ch 035Dh 035Eh 035Fh 0360h 0361h 0362h 0363h 0364h 0365h 0366h 0367h 0368h 0369h 036Ah 036Bh 036Ch 036Dh 036Eh 036Fh 0370h 0371h 0372h 0373h 0374h 0375h 0376h 0377h 0378h 0379h 037Ah 037Bh 037Ch 037Dh 037Eh 037Fh
Register
Symbol
Page
Interrupt Factor Select Register 2 Interrupt Factor Select Register
IFSR2A IFSR
75 75
UART0 Special Mode Register 4 UART0 Special Mode Register 3 UART0 Special Mode Register 2 UART0 Special Mode Register UART1 Special Mode Register 4 UART1 Special Mode Register 3 UART1 Special Mode Register 2 UART1 Special Mode Register UART2 Special Mode Register 4 UART2 Special Mode Register 3 UART2 Special Mode Register 2 UART2 Special Mode Register UART2 Transmit/Receive Mode Register UART2 Bit Rate Generator UART2 Transmit Buffer Register UART2 Transmit/Receive Control Register 0 UART2 Transmit/Receive Control Register 1 UART2 Receive Buffer Register
U0SMR4 U0SMR3 U0SMR2 U0SMR U1SMR4 U1SMR3 U1SMR2 U1SMR U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG U2TB U2C0 U2C1 U2RB
129 128 128 127 129 128 128 127 129 128 128 127 124 124 123 125 126 123
Address 0380h 0381h 0382h 0383h 0384h 0385h 0386h 0387h 0388h 0389h 038Ah 038Bh 038Ch 038Dh 038Eh 038Fh 0390h 0391h 0392h 0393h 0394h 0395h 0396h 0397h 0398h 0399h 039Ah 039Bh 039Ch 039Dh 039Eh 039Fh 03A0h 03A1h 03A2h 03A3h 03A4h 03A5h 03A6h 03A7h 03A8h 03A9h 03AAh 03ABh 03ACh 03ADh 03AEh 03AFh 03B0h 03B1h 03B2h 03B3h 03B4h 03B5h 03B6h 03B7h 03B8h 03B9h 03BAh 03BBh 03BCh 03BDh 03BEh 03BFh
Register Count Start Flag Clock Prescaler Reset Fag One-Shot Start Flag Trigger Select Register Up-Down Flag Timer A0 Register Timer A1 Register Timer A2 Register
Symbol TABSR CPSRF ONSF TRGSR UDF TA0 TA1 TA2
Page 96, 112 98, 112 97 97 96 95 95 95
Timer B0 Register Timer B1 Register Timer B2 Register Timer A0 Mode Register Timer A1 Mode Register Timer A2 Mode Register
TB0 TB1 TB2 TA0MR TA1MR TA2MR
111 111 111 95 95 95
Timer B0 Mode Register Timer B1 Mode Register Timer B2 Mode Register
TB0MR TB1MR TB2MR
111 111 111
UART0 Transmit/Receive Mode Register UART0 Bit Rate Generator UART0 Transmit Buffer Register UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register UART1 Transmit/Receive Mode Register UART1 Bit Rate Generator UART1 Transmit Buffer Register UART1 Transmit/Receive Control Register 0 UART1 Transmit/Receive Control Register 1 UART1 Receive Buffer Register UART Transmit/Receive Control Register 2
U0MR U0BRG U0TB U0C0 U0C1 U0RB U1MR U1BRG U1TB U1C0 U1C1 U1RB UCON
124 124 123 125 126 123 124 124 123 125 126 123 127
DMA0 Request Factor Select Register DMA1 Request Factor Select Register CRC Data Register CRC Input Register
DM0SL DM1SL CRCD CRCIN
83 84 180 180
NOTES: 1. Blank columns are all reserved space. No access is allowed.
B-2
Address 03C0h 03C1h 03C2h 03C3h 03C4h 03C5h 03C6h 03C7h 03C8h 03C9h 03CAh 03CBh 03CCh 03CDh 03CEh 03CFh 03D0h 03D1h 03D2h 03D3h 03D4h 03D5h 03D6h 03D7h 03D8h 03D9h 03DAh 03DBh 03DCh 03DDh 03DEh 03DFh 03E0h 03E1h 03E2h 03E3h 03E4h 03E5h 03E6h 03E7h 03E8h 03E9h 03EAh 03EBh 03ECh 03EDh 03EEh 03EFh 03F0h 03F1h 03F2h 03F3h 03F4h 03F5h 03F6h 03F7h 03F8h 03F9h 03FAh 03FBh 03FCh 03FDh 03FEh 03FFh
Register A/D Register 0 A/D Register 1 A/D Register 2 A/D Register 3 A/D Register 4 A/D Register 5 A/D Register 6 A/D Register 7
Symbol AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
Page 171 171 171 171 171 171 171 171
A/D Control Register 2 A/D Control Register 0 A/D Control Register 1
ADCON2 ADCON0 ADCON1
171 170 170
Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P2 Register Port P3 Register Port P2 Direction Register Port P3 Direction Register Port P4 Register Port P5 Register Port P4 Direction Register Port P5 Direction Register Port P6 Register Port P7 Register Port P6 Direction Register Port P7 Direction Register Port P8 Register Port P9 Register Port P8 Direction Register Port P9 Direction Register Port P10 Register Port P10 Direction Register
P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 P5 PD4 PD5 P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 PD10
189 189 188 188 189 189 188 188 189 189 188 188 189 189 188 188 189 189 188 188 189 188
Pull-Up Control Register 0 Pull-Up Control Register 1 Pull-Up Control Register 2 Port Control Register
PUR0 PUR1 PUR2 PCR
190 190 191 191
NOTES: 1. Blank columns are all reserved space. No access is allowed.
B-3
M16C/30P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.
Overview
The M16C/30P Group of single-chip microcomputers is built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core and is packaged in a 100-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 1 Mbyte of address space, they are capable of executing instructions at high speed. In addition, these microcomputers contain a multiplier and DMAC which combined with fast instruction processing capability, make it suitable for control of various OA, communication, and industrial equipment which requires high-speed arithmetic/ logic operations.
1.1
Applications
Audio, cameras, TV, home appliance, office/communications/portable/industrial equipment, etc.
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Page 1 of 291
M16C/30P Group
1. Overview
1.2
Performance Outline
Table 1.1 lists Performance Outline of M16C/30P Group. Table 1.1 CPU Performance Outline of M16C/30P Group
Item Performance Number of Basic Instructions 91 instructions Minimum Instruction 62.5ns(f(XIN)=16MHz, VCC1=VCC2=3.0 to 5.5V, no Execution Time wait) 100ns(f(XIN)=10MHz, VCC1=VCC2=2.7 to 5.5V, no wait) Operation Mode Single-chip, memory expansion and microprocessor mode Memory Space 1 Mbyte Memory Capacity See Table 1.2 Product List Peripheral Port Input/Output : 87 pins, Input : 1 pin Function Multifunction Timer Timer A : 16 bits x 3 channels, Timer B : 16 bits x 3 channels Serial Interface 1 channels Clock synchronous, UART, I2CBus(1), IEBus(2) 2 channels Clock synchronous, UART, I2CBus(1) A/D Converter 10-bit A/D converter: 1 circuit, 18 channels DMAC 2 channels CRC Calculation Circuit CCITT-CRC Watchdog Timer 15 bits x 1 channel (with prescaler) Interrupt Internal: 20 sources, External: 7 sources, Software: 4 sources, Priority level: 7 levels Clock Generating Circuit 2 circuits Main clock generation circuit (*), Subclock generation circuit (*), (*)Equipped with a built-in feedback resistor. Electric Supply Voltage VCC1=VCC2=3.0 to 5.5 V (f(XIN)=16MHz) Characteristics VCC1=VCC2=2.7 to 5.5 V (f(XIN)=10MHz, no wait) Power Consumption 10 mA (VCC1=VCC2=5V, f(XIN)=16MHz) 8 mA (VCC1=VCC2=3V, f(XIN)=10MHz) 1.8 A (VCC1=VCC2=3V, f(XCIN)=32kHz, wait mode) 0.7 A(VCC1=VCC2=3V, stop mode) One time flash Program Supply Voltage 3.30.3 V or 5.00.5 V version Flash memory Program/Erase Supply 3.30.3 V or 5.00.5 V version Voltage Program and Erase 100 times (all area) Endurance Operating Ambient Temperature -20 to 85C, -40 to 85C Package 100-pin plastic mold QFP, LQFP
NOTES: 1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V. 2. IEBus is a registered trademark of NEC Electronics Corporation. 3. Use the M16C/30P on VCC1 = VCC2.
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M16C/30P Group
1. Overview
1.3
Block Diagram
Figure 1.1 is a M16C/30P Group Block Diagram.
8
8
8
8
8
8
8
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Port P7
8
Internal peripheral functions
A/D converter
Timer (16-bit) Output (timer A): 3 Input (timer B): 3
(10 bits X 18 channels)
UART or clock synchronous serial I/O
System clock generation circuit XIN-XOUT XCIN-XCOUT
Port P8
7
(3 channels)
Port P8_5
CRC arithmetic circuit (CCITT ) (Polynomial : X16+X12+X5+1)
M16C/60 series16-bit CPU core Watchdog timer
(15 bits)
R0H R1H R2 R3 A0 A1 FB R0L R1L SB USP ISP INTB PC FLG
Memory
Port P9
ROM (1) RAM (2)
8
DMAC
(2 channels)
Port P10
8
Multiplier
NOTES : 1. ROM size depends on microcomputer type. 2. RAM size depends on microcomputer type.
Figure 1.1
M16C/30P Group Block Diagram
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Page 3 of 291
M16C/30P Group
1. Overview
1.4
Product List
Table 1.2 lists the M16C/30P group products and Figure 1.2 shows the Part No., Memory Size, and Package. Table 1.4 lists Product Code of MASK ROM version for M16C/30P. Figure 1.3 shows the Marking Diagram of Mask ROM Version for M16C/30P (Top View). Table 1.5 lists Product Code of One Time Flash version, Flash Memory version, and ROM-less version for M16C/30P. Figure 1.4 shows the Marking Diagram of One Time Flash version, Flash Memory version, and ROM-less Version for M16C/30P (Top View). Please specify the marking for M16C30P (MASK ROM version) when placing an order for ROM. Table 1.2 Product List (1)
ROM Capacity 96 Kbytes 128 Kbytes 160 Kbytes 192 Kbytes 96 Kbytes (D) 128 Kbytes (D) 160 Kbytes (D) (D) (D) 192 Kbytes (D) (D) (D) (D) (D) (D) 128 Kbytes (D) 160 Kbytes (D) (D) (D) 192 Kbytes (D) (D) (D) (D) (D) 6 Kbytes 12 Kbytes 6 Kbytes 12 Kbytes 256 Kbytes 12 Kbytes 6 Kbytes 12 Kbytes 6 Kbytes 12 Kbytes 256 Kbytes 96 Kbytes 12 Kbytes 5 Kbytes 5 Kbytes 6 Kbytes RAM Capacity 5 Kbytes package code PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A
(1)
As of March 2007 Remarks Mask ROM version
Part No. M30302MAP-XXXFP M30302MAP-XXXGP M30302MCP-XXXFP M30302MCP-XXXGP M30302MDP-XXXFP M30302MDP-XXXGP M30302MEP-XXXFP M30302MEP-XXXGP M30302GAPFP M30302GAPGP M30302GCPFP M30302GCPGP M30302GDPFP M30302GDPGP M30304GDPFP M30304GDPGP M30302GEPFP M30302GEPGP M30304GEPFP M30304GEPGP M30302GGPFP M30302GGPGP M30302GAP-XXXFP M30302GAPvGP M30302GCP-XXXFP M30302GCP-XXXGP M30302GDP-XXXFP M30302GDP-XXXGP M30304GDP-XXXFP M30304GDP-XXXGP M30302GEP-XXXFP M30302GEP-XXXGP M30304GEP-XXXFP M30304GEP-XXXGP M30302GGP-XXXFP M30302GGP-XXXGP
One Time Flash version (blank product)
One Time Flash version (factory programmed product)
(D): Under development (P): Under planning NOTES: 1. Previous package codes are as follows. PRQP0100JB-A : 100P6S-A, PLQP0100KB-A : 100P6Q-A 2. Block A (4-Kbytes space) is available in flash memory version.
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M16C/30P Group Table 1.3 Product List (2)
ROM Capacity 96 K + 4 Kbytes 128 K + 4 Kbytes 192 K + 4 Kbytes 6 Kbytes 6 Kbytes RAM Capacity 5 Kbytes package code (1) PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A
1. Overview
As of March 2007 Remarks Flash memory version(2)
Part No. M30302FAPFP M30302FAPGP M30302FCPFP M30302FCPGP M30302FEPFP M30302FEPGP M30302SPFP M30302SPGP
ROM-less version
(D): Under development (P): Under planning NOTES: 1. Previous package codes are as follows. PRQP0100JB-A : 100P6S-A, PLQP0100KB-A : 100P6Q-A 2. Block A (4-Kbytes space) is available in flash memory version.
Part No.
M3030 2 M E P- XXX HP
Package type: FP : Package PRQP0100JB-A (100P6S-A) GP : Package PLQP0100KB-A (100P6Q-A) ROM No. M16C/30P Group ROM A C D E G capacity: : 96 Kbytes : 128 Kbytes : 160 Kbytes : 192 Kbytes : 256 Kbytes
Memory type: M : Mask ROM version G : One Time Flash version F : Flash Memory version S : ROM-less version Shows RAM capacity, pin count, etc (The value itself has no specific meaning) M16C/30 Series M16C Family
Figure 1.2
Part No., Memory Size, and Package
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M16C/30P Group
1. Overview
Table 1.4
Product Code U1 U4
Product Code of MASK ROM version for M16C/30P
Package Lead-free Operating Ambient Temperature -20C to 85C -40C to 85C
PRQP0100JB-A (100P6S-A)
1. Standard Renesas Mark
M1 6C M3 0 3 0 2 M D P - X X X F P A U1 XXXXXXX
Part No. (See Figure 1.2 Part No., Memory Size, and Package) Chip version, product code and date code A : Shows chip version. Henceforth, whenever it changes a version, it continues with A, B, and C. U1 : Shows Product code. (See table 1.3 Product Code) XXXXXXX : Seven digits
2. Customer's Parts Number + Renesas catalog name
M3 0 3 0 2 M D P - X X X F P A U1 M1 6 C X X X X X X X
Part No. (See Figure 1.2 Part No., Memory Size, and Package) Chip version and product code A : Shows chip version. Henceforth, whenever it changes a version, it continues with A, B, and C. U1 : Shows Product code. (See table 1.3 Product Code) Date code seven digits
PLQP0100KB-A (100P6Q-A)
1. Standard Renesas Mark
M1 6C M 3 0 3 0 2 MD P - X X XGP A U 1 XXXXXXX
Part No. (See Figure 1.2 Part No., Memory Size, and Package) Chip version, product code and date code A : Shows chip version. Henceforth, whenever it changes a version, it continues with A, B, and C. U1 : Shows Product code. (See table 1.3 Product Code) XXXXXXX : Seven digits
2. Customer's Parts Number + Renesas catalog name
M 3 0 3 0 2 MD P A U1 - X X XGP M1 6 C XXXXXXX
Part No. (See Figure 1.2 Part No., Memory Size, and Package) Chip version and product code A : Shows chip version. Henceforth, whenever it changes a version, it continues with A, B, and C. U1 : Shows Product code. (See table 1.3 Product Code) Date code seven digits
NOTES: 1. Refer to the mark specification form for details of the Mask ROM version marking.
Figure 1.3
Marking Diagram of Mask ROM Version for M16C/30P (Top View) Page 6 of 291
Rev.1.22 Mar 29, 2007 REJ09B0179-0122
M16C/30P Group
1. Overview
Table 1.5
Product Code of One Time Flash version, Flash Memory version, and ROM-less version for M16C/30P
Internal ROM
Product Code One Time Flash version Flash Memory version ROM-less version U3 U5 U3 U5 U3 U5
Package
Program and Erase Endurance 0 100
-
Temperature Range 0C to 60C
Operating Ambient Temperature -40C to 85C -20C to 85C -40C to 85C -20C to 85C -40C to 85C -20C to 85C
Leadfree Leadfree Leadfree
0C to 60C -
NOTES:The one time flash version can be written once only.
PRQP0100JB-A (100P6S-A) M1 M3 03 0 2SP A XXXXX 6 F U X C P 3 X
Part No. (See Figure 1.2 Part No., Memory Size, and Package) Chip version and product code A : Shows chip version. Henceforth, whenever it changes a version, it continues with A, B, and C. U3 : Shows Product code. (See table 1.3 Product Code) Date code seven digits
PLQP0100KB-A (100P6Q-A)
M1 6C M 3 0 3 0 2 S PGP A U3 XXXXXXX
Part No. (See Figure 1.2 Part No., Memory Size, and Package) Chip version and product code A : Shows chip version. Henceforth, whenever it changes a version, it continues with A, B, and C. U3 : Shows Product code. (See table 1.3 Product Code) Date code seven digits
The product without marking of chip version of One Time Flash version, Flash Memory version, and the ROMless version corresponds to the chip version "A".
Figure 1.4
Marking Diagram of One Time Flash version, Flash Memory version, and ROM-less Version for M16C/30P (Top View)
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M16C/30P Group
1. Overview
1.5
Pin Configuration
Figures 1.5 to 1.6 show the pin configurations (top view).
PIN CONFIGURATION (top view)
P1_0/D8 P1_1/D9 P1_2/D10 P1_3/D11 P1_4/D12 P1_5/D13/INT3 P1_6/D14/INT4 P1_7/D15 P2_0/A0 P2_1/A1 P2_2/A2 P2_3/A3 P2_4/A4 P2_5/A5 P2_6/A6 P2_7/A7 VSS P3_0/A8 VCC2 P3_1/A9 P3_2/A10 P3_3/A11 P3_4/A12 P3_5/A13 P3_6/A14 P3_7/A15 P4_0/A16 P4_1/A17 P4_2/A18 P4_3/A19
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P0_7/AN0_7/D7 P0_6/AN0_6/D6 P0_5/AN0_5/D5 P0_4/AN0_4/D4 P0_3/AN0_3/D3 P0_2/AN0_2/D2 P0_1/AN0_1/D1 P0_0/AN0_0/D0 P10_7/AN7/KI3 P10_6/AN6/KI2 P10_5/AN5/KI1 P10_4/AN4/KI0 P10_3/AN3 P10_2/AN2 P10_1/AN1 AVSS P10_0/AN0 VREF AVCC P9_7/ADTRG
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
M16C/30P Group
P4_4/CS0 P4_5/CS1 P4_6/CS2 P4_7/CS3 P5_0/WRL/WR P5_1/WRH/BHE P5_2/RD P5_3/BCLK P5_4/HLDA P5_5/HOLD P5_6/ALE P5_7/RDY/CLKOUT P6_0/CTS0/RTS0 P6_1/CLK0 P6_2/RXD0/SCL0 P6_3/TXD0/SDA0 P6_4/CTS1/RTS1/CTS0/CLKS1 P6_5/CLK1 P6_6/RXD1/SCL1 P6_7/TXD1/SDA1
NOTES: 1. P7_0 and P7_1 are N channel open-drain output pins. 2. Use the M16C/30P on VCC1=VCC2.
Figure 1.5
Pin Configuration (Top View)
Rev.1.22 Mar 29, 2007 REJ09B0179-0122
P9_6/ANEX1 P9_5/ANEX0 P9_4 P9_3 P9_2/TB2IN P9_1/TB1IN P9_0/TB0IN BYTE CNVSS P8_7/XCIN P8_6/XCOUT RESET XOUT VSS XIN VCC1 P8_5/NMI P8_4/INT2 P8_3/INT1 P8_2/INT0 P8_1 P8_0 P7_7 P7_6 P7_5/TA2IN P7_4/TA2OUT P7_3/CTS2/RTS2/TA1IN P7_2/CLK2/TA1OUT P7_1/RXD2/SCL2/TA0IN (1) P7_0/TXD2/SDA2/TA0OUT (1)
Package : PRQP0100JB-A (100P6S-A)
Page 8 of 291
M16C/30P Group
1. Overview
PIN CONFIGURATION (top view)
P1_3/D11 P1_4/D12 P1_5/D13/INT3 P1_6/D14/INT4 P1_7/D15 P2_0/A0 P2_1/A1 P2_2/A2 P2_3/A3 P2_4/A4 P2_5/A5 P2_6/A6 P2_7/A7 VSS P3_0/A8 VCC2 P3_1/A9 P3_2/A10 P3_3/A11 P3_4/A12 P3_5/A13 P3_6/A14 P3_7/A15 P4_0/A16 P4_1/A17
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P1_2/D10 P1_1/D9 P1_0/D8 P0_7/AN0_7/D7 P0_6/AN0_6/D6 P0_5/AN0_5/D5 P0_4/AN0_4/D4 P0_3/AN0_3/D3 P0_2/AN0_2/D2 P0_1/AN0_1/D1 P0_0/AN0_0/D0 P10_7/AN7/KI3 P10_6/AN6/KI2 P10_5/AN5/KI1 P10_4/AN4/KI0 P10_3/AN3 P10_2/AN2 P10_1/AN1 AVSS P10_0/AN0 VREF AVCC P9_7/ADTRG P9_6/ANEX1 P9_5/ANEX0
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
50 49 48 47 46 45 44 43 42 41 40
M16C/30P Group
39 38 37 36 35 34 33 32 31 30 29 28 27 26
P4_2/A18 P4_3/A19 P4_4/CS0 P4_5/CS1 P4_6/CS2 P4_7/CS3 P5_0/WRL/WR P5_1/WRH/BHE P5_2/RD P5_3/BCLK P5_4/HLDA P5_5/HOLD P5_6/ALE P5_7/CLKOUT P6_0/CTS0/RTS0 P6_1/CLK0 P6_2/RXD0/SCL0 P6_3/TXD0/SDA0 P6_4/CTS1/RTS1/CTS0/CLKS1 P6_5/CLK1 P6_6/RXD1/SCL1 P6_7/TXD1/SDA1 P7_0/TXD2/SDA2/TA0OUT(1) P7_1/RXD2/SCL2/TA0IN(1) P7_2/CLK2/TA1OUT
NOTES: 1. P7_0 and P7_1 are N channel open-drain output pins. 2. Use the M16C/30P on VCC1=VCC2.
Figure 1.6
Pin Configuration (Top View)
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Page 9 of 291
P9_4 P9_3 P9_2/TB2IN P9_1/TB1IN P9_0/TB0IN BYTE CNVSS P8_7/XCIN P8_6/XCOUT RESET XOUT VSS XIN VCC1 P8_5/NMI P8_4/INT2 P8_3/INT1 P8_2/INT0 P8_1 P8_0 P7_7 P7_6 P7_5/TA2IN P7_4/TA2OUT P7_3/CTS2/RTS2/TA1IN
Package : PLQP0100KB-A (100P6Q-A)
M16C/30P Group
1. Overview
Table 1.6
Pin No. FP GP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Pin Characteristics (1)
Control Pin Port
P9_6 P9_5 P9_4 P9_3 P9_2 P9_1 P9_0 BYTE CNVSS XCIN XCOUT RESET XOUT VSS XIN VCC1 P8_5 P8_4 P8_3 P8_2 P8_1 P8_0 P7_7 P7_6 P7_5 P7_4 P7_3 P7_2 P7_1 P7_0 P6_7 P6_6 P6_5 P6_4 P6_3 P6_2 P6_1 P6_0 P5_7 P5_6 P5_5 P5_4 P5_3 P5_2 P5_1 P5_0 P4_7 P4_6 P4_5 P4_4 TA2IN TA2OUT TA1IN TA1OUT TA0IN TA0OUT CTS2/RTS2 CLK2 RXD2/SCL2 TXD2/SDA2 TXD1/SDA1 RXD1/SCL1 CLK1 CTS1/RTS1/CTS0/CLKS1 TXD0/SDA0 RXD0/SCL0 CLK0 CTS0/RTS0 RDY/CLKOUT ALE HOLD HLDA BCLK RD WRH/BHE WRL/WR CS3 CS2 CS1 CS0 NMI INT2 INT1 INT0 P8_7 P8_6 TB2IN TB1IN TB0IN
Interrupt Pin
Timer Pin
UART Pin
Analog Pin
ANEX1 ANEX0
Bus Control Pin
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M16C/30P Group
1. Overview
Table 1.7
Pin Characteristics (2)
Port
P4_3 P4_2 P4_1 P4_0 P3_7 P3_6 P3_5 P3_4 P3_3 P3_2 P3_1 P3_0 P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0 P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 P1_1 P1_0 P0_7 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0 P10_7 P10_6 P10_5 P10_4 P10_3 P10_2 P10_1 P10_0 KI3 KI2 KI1 KI0 AN0_7 AN0_6 AN0_5 AN0_4 AN0_3 AN0_2 AN0_1 AN0_0 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 INT4 INT3
Pin No. Control Pin FP GP
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 49 50 51 52 53 54 55 56 57 58 59 60 VCC2 61 62 VSS 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 AVSS 95 96 VREF 97 AVCC 98
Interrupt Pin
Timer Pin
UART Pin
Analog Pin
Bus Control Pin
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
P9_7
ADTRG
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M16C/30P Group
1. Overview
1.6
Pin Description
Pin Description (1)
Pin Name VCC1, VCC2 VSS AVCC AVSS RESET CNVSS I/O Type Description I Apply 2.7 to 5.5 V to the VCC1 and VCC2 pins and 0 V to the VSS pin. The VCC apply condition is that VCC1 = VCC2. I Applies the power supply for the A/D converter. Connect the AVCC pin to VCC1. Connect the AVSS pin to VSS. I The microcomputer is in a reset state when applying "L" to the this pin. I Switches processor mode. Connect this pin to VSS to when after a reset to start up in single-chip mode. Connect this pin to VCC1 to start up in microprocessor mode. I Switches the data bus in external memory space. The data bus is 16 bits long when the this pin is held "L" and 8 bits long when the this pin is held "H". Set it to either one. Connect this pin to VSS when an single-chip mode. I/O Inputs and outputs data (D0 to D7) when these pins are set as the separate bus. I/O Inputs and outputs data (D8 to D15) when external 16-bit data bus is set as the separate bus. O Output address bits (A0 to A19). O O Output CS0 to CS3 signals. CS0 to CS3 are chip-select signals to specify an external space. Output WRL, WRH, (WR, BHE), RD signals. WRL and WRH or BHE and WR can be switched by program. * WRL, WRH and RD are selected The WRL signal becomes "L" by writing data to an even address in an external memory space. The WRH signal becomes "L" by writing data to an odd address in an external memory space. The RD pin signal becomes "L" by reading data in an external memory space. * WR, BHE and RD are selected The WR signal becomes "L" by writing data in an external memory space. The RD signal becomes "L" by reading data in an external memory space. The BHE signal becomes "L" by accessing an odd address. Select WR, BHE and RD for an external 8-bit data bus. ALE is a signal to latch the address. While the HOLD pin is held "L", the microcomputer is placed in a hold state. In a hold state, HLDA outputs a "L" signal. While applying a "L" signal to the RDY pin, the microcomputer is placed in a wait state.
Table 1.8
Signal Name Power supply input Analog power supply input Reset input CNVSS
External data bus width select input
BYTE
Bus control pins
D0 to D7 D8 to D15 A0 to A19 CS0 to CS3 WRL/WR WRH/BHE RD
ALE HOLD HLDA RDY I : Input O : Output
O I O I
I/O : Input and output
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M16C/30P Group
1. Overview
Table 1.9
Signal Name Main clock input Main clock output Sub clock input Sub clock output Clock output INT interrupt input NMI interrupt input Key input interrupt input Timer A
Pin Description (2)
Pin Name XIN XOUT XCIN XCOUT CLKOUT INT0 to INT4 NMI KI0 to KI3 TA0OUT to TA2OUT TA0IN to TA2IN TB0IN to TB2IN CTS0 to CTS2 RTS0 to RTS2 CLK0 to CLK2 RXD0 to RXD2 TXD0 to TXD2 CLKS1 SDA0 to SDA2 SCL0 to SCL2 I/O Type I O I O O I I I I/O I I I O I/O I O O I/O I/O I I I I/O I I/O Description I/O pins for the main clock generation circuit. Connect a ceramic resonator or crystal oscillator between XIN and XOUT. To use the external clock, input the clock from XIN and leave XOUT open. I/O pins for a sub clock oscillation circuit. Connect a crystal oscillator between XCIN and XCOUT. To use the external clock, input the clock from XCIN and leave XCOUT open. The clock of the same cycle as fC, f8, or f32 is outputted. Input pins for the INT interrupt. Input pin for the NMI interrupt. Input pins for the key input interrupt. These are timer A0 to timer A2 I/O pins. (however, the output of TA0OUT for the N-channel open drain output.) These are timer A0 to timer A2 input pins. These are timer B0 to timer B2 input pins. These are send control input pins. These are receive control output pins. These are transfer clock I/O pins. These are serial data input pins. These are serial data output pins. (however, TXD2 for the N-channel open drain output.) This is output pin for transfer clock output from multiple pins function. These are serial data I/O pins. (however, SDA2 for the N-channel open drain output.) These are transfer clock I/O pins. (however, SCL2 for the N-channel open drain output.) Applies the reference voltage for the A/D converter. Analog input pins for the A/D converter. This is an A/D trigger input pin. This is the extended analog input pin for the A/D converter, and is the output in external op-amp connection mode. This is the extended analog input pin for the A/D converter. 8-bit I/O ports in CMOS, having a direction register to select an input or output. Each pin is set as an input port or output port. An input port can be set for a pull-up or for no pull-up in 4-bit unit by program. (however, P7_0 and P7_1 for the N-channel open drain output.)
Timer B Serial interface
I2C mode
Reference voltage input A/D converter
VREF AN0 to AN7, AN0_0 to AN0_7 ADTRG ANEX0 ANEX1 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P9_0 to P9_7, P10_0 to P10_7 P8_0 to P8_4, P8_6, P8_7 P8_5
I/O port
I/O I
I/O ports having equivalent functions to P0. Input pin for the NMI interrupt. Pin states can be read by the P8_5 bit in the P8 register.
Input port I : Input
O : Output
I/O : Input and output
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M16C/30P Group
2. Central Processing Unit (CPU)
2.
Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. There are two register banks.
b31 b15 b8 b7 b0
R2 R3
R0H R1H R2 R3 A0 A1 FB
R0L R1L Data Registers (1)
Address Registers (1) Frame Base Registers (1)
b0
b19
b15
INTBH
INTBL
Interrupt Table Register
b19
b0
PC
b15 b0
Program Counter
USP ISP SB
b15 b0
User Stack Pointer Interrupt Stack Pointer Static Base Register
FLG
b15 b8 b7 b0
Flag Register
IPL
UI
OB S Z DC
Carry Flag Debug Flag Zero Flag Sign Flag Register Bank Select Flag Overflow Flag Interrupt Enable Flag Stack Pointer Select Flag Reserved Area Processor Interrupt Priority Level Reserved Area
NOTES: 1. These registers comprise a register bank. There are two register banks.
Figure 2.1
Central Processing Unit Register
2.1
Data Registers (R0, R1, R2 and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to R3 are the same as R0. The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers. R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-bit data register (R2R0). R3R1 is the same as R2R0.
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M16C/30P Group
2. Central Processing Unit (CPU)
2.2
Address Registers (A0 and A1)
The register A0 consists of 16 bits, and is used for address register indirect addressing and address register relative addressing. They also are used for transfers and logic/logic operations. A1 is the same as A0. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5
Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7
Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8
Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
2.8.1
Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
2.8.2
Debug Flag (D Flag)
The D flag is used exclusively for debugging purpose. During normal use, it must be set to "0".
2.8.3
Zero Flag (Z Flag)
This flag is set to "1" when an arithmetic operation resulted in 0; otherwise, it is "0".
2.8.4
Sign Flag (S Flag)
This flag is set to "1" when an arithmetic operation resulted in a negative value; otherwise, it is "0".
2.8.5
Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is "0" ; register bank 1 is selected when this flag is "1".
2.8.6
Overflow Flag (O Flag)
This flag is set to "1" when the operation resulted in an overflow; otherwise, it is "0".
2.8.7
Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt. Maskable interrupts are disabled when the I flag is "0", and are enabled when the I flag is "1". The I flag is cleared to "0" when the interrupt request is accepted.
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M16C/30P Group
2. Central Processing Unit (CPU)
2.8.8
Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is "0"; USP is selected when the U flag is "1". The U flag is cleared to "0" when a hardware interrupt request is accepted or an INT instruction for software interrupt Nos. 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than IPL, the interrupt is enabled.
2.8.10
Reserved Area
When write to this bit, write "0". When read, its content is indeterminate.
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M16C/30P Group
3. Memory
3.
Memory
Figure 3.1 is a Memory Map of the M16C/30P group. The address space extends the 1 Mbyte from address 00000h to FFFFFh. The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a 64-Kbyte internal ROM is allocated to the addresses from F0000h to FFFFFh. The fixed interrupt vector table is allocated to the addresses from FFFDCh to FFFFFh. Therefore, store the start address of each interrupt routine here. The internal RAM is allocated in an upper address direction beginning with address 00400h. For example, a 5-Kbyte internal RAM is allocated to the addresses from 00400h to 017FFh. In addition to storing data, the internal RAM also stores the stack used when calling subroutines and when interrupts are generated. The SFR is allocated to the addresses from 00000h to 003FFh. Peripheral function control registers are located here. Of the SFR, any area which has no functions allocated is reserved for future use and cannot be used by users. The special page vector table is allocated to the addresses from FFE00h to FFFDBh. This vector is used by the JMPS or JSRS instruction. For details, refer to the M16C/60 and M16C/20 Series Software Manual.
00000h SFR 00400h Internal RAM XXXXXh Reserved area 0F000h Internal ROM (data area) (3, 4) 0FFFFh 10000h External area 27000h Reserved area
Internal RAM Size 5 Kbytes 6 Kbytes 12 Kbytes Address XXXXXh 017FFh 01BFFh 033FFh Size 96 Kbytes 128 Kbytes 160 Kbytes 192 Kbytes 256 Kbytes Internal ROM
(5)
(1)
FFE00h
Special page vector table
FFFDCh
28000h External area D0000h Reserved area (2, 4) YYYYYh Internal ROM (program area) (5) FFFFFh FFFFFh
Undefined instruction
Overflow
BRK instruction Address match Single step Watchdog timer DBC NMI Reset
Address YYYYYh E8000h E0000h D8000h D0000h C0000h(6)
NOTES: 1. During memory expansion and microprocessor modes, can be used. 2. In memory expansion mode, can be used. 3. As for the flash memory version, 4-Kbyte space (block A) exists. 4. Shown here is a memory map for the case where the PM10 bit in the PM1 register is "1" . 5. When using the masked ROM version, write nothing to internal ROM area. 6. When the PM13 bit is set to "0", the address of Internal ROM becomes D0000h, and when the PM13 bit is set to "1", the address becomes C0000h.
Figure 3.1
Memory Map
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M16C/30P Group
4. Special Function Register (SFR)
4.
Special Function Register (SFR)
SFR(Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.5 list the SFR information. Table 4.1
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh
SFR Information (1) (1)
Register Symbol After Reset
Processor Mode Register 0 (2) Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 Chip Select Control Register Address Match Interrupt Enable Register Protect Register
PM0 PM1 CM0 CM1 CSR AIER PRCR
00000000b(CNVSS pin is "L") 00000011b(CNVSS pin is "H")
00XXX0X0b 01001000b 00100000b 00000001b XXXXXX00b XX000000b
Watchdog Timer Start Register Watchdog Timer Control Register Address Match Interrupt Register 0
WDTS WDC RMAD0
XXh 00XXXXXXb 00h 00h X0h 00h 00h X0h
Address Match Interrupt Register 1
RMAD1
DMA0 Source Pointer
SAR0
XXh XXh XXh XXh XXh XXh XXh XXh
DMA0 Destination Pointer
DAR0
DMA0 Transfer Counter
TCR0
DMA0 Control Register
DM0CON
00000X00b
DMA1 Source Pointer
SAR1
XXh XXh XXh XXh XXh XXh XXh XXh
DMA1 Destination Pointer
DAR1
DMA1 Transfer Counter
TCR1
DMA1 Control Register
DM1CON
00000X00b
NOTES: 1. The blank areas are reserved and cannot be accessed by users. 2. The PM00 and PM01 bits do not change at software reset. X : Nothing is mapped to this bit
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M16C/30P Group Table 4.2
Address 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h to 01AFh 01B0h 01B1h 01B2h 01B3h 01B4h 01B5h 01B6h 01B7h 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh 01BFh 01C0h to 024Fh 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025Ah 025Bh 025Ch 025Dh 025Eh 025Fh 0260h to 033Fh
4. Special Function Register (SFR) SFR Information (2) (1)
Register Symbol After Reset
INT3 Interrupt Control Register UART1 BUS Collision Detection Interrupt Control Register UART0 BUS Collision Detection Interrupt Control Register INT4 Interrupt Control Register UART2 Bus Collision Detection Interrupt Control Register DMA0 Interrupt Control Register DMA1 Interrupt Control Register Key Input Interrupt Control Register A/D Conversion Interrupt Control Register UART2 Transmit Interrupt Control Register UART2 Receive Interrupt Control Register UART0 Transmit Interrupt Control Register UART0 Receive Interrupt Control Register UART1 Transmit Interrupt Control Register UART1 Receive Interrupt Control Register Timer A0 Interrupt Control Register Timer A1 Interrupt Control Register Timer A2 Interrupt Control Register
INT3IC U1BCNIC U0BCNIC INT4IC BCNIC DM0IC DM1IC KUPIC ADIC S2TIC S2RIC S0TIC S0RIC S1TIC S1RIC TA0IC TA1IC TA2IC
XX00X000b XXXXX000b XXXXX000b XX00X000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b
Timer B0 Interrupt Control Register Timer B1 Interrupt Control Register Timer B2 Interrupt Control Register INT0 Interrupt Control Register INT1 Interrupt Control Register INT2 Interrupt Control Register
TB0IC TB1IC TB2IC INT0IC INT1IC INT2IC
XXXXX000b XXXXX000b XXXXX000b XX00X000b XX00X000b XX00X000b
Flash Memory Control Register 1 (2) Flash Memory Control Register 0 (3)
FMR1 FMR0
0X00XX0Xb 00000001b
Peripheral Clock Select Register
PCLKR
00000011b
NOTES: 1. The blank areas are reserved and cannot be accessed by users. 2. This register is included in the flash memory version. 3. This register is included in the flash memory version and one time flash version.
X : Nothing is mapped to this bit
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M16C/30P Group Table 4.3
Address 0340h 0341h 0342h 0343h 0344h 0345h 0346h 0347h 0348h 0349h 034Ah 034Bh 034Ch 034Dh 034Eh 034Fh 0350h 0351h 0352h 0353h 0354h 0355h 0356h 0357h 0358h 0359h 035Ah 035Bh 035Ch 035Dh 035Eh 035Fh 0360h 0361h 0362h 0363h 0364h 0365h 0366h 0367h 0368h 0369h 036Ah 036Bh 036Ch 036Dh 036Eh 036Fh 0370h 0371h 0372h 0373h 0374h 0375h 0376h 0377h 0378h 0379h 037Ah 037Bh 037Ch 037Dh 037Eh 037Fh
4. Special Function Register (SFR) SFR Information (3) (1)
Register Symbol After Reset
Interrupt Factor Select Register 2 Interrupt Factor Select Register
IFSR2A IFSR
00XXXXXXb 00h
UART0 Special Mode Register 4 UART0 Special Mode Register 3 UART0 Special Mode Register 2 UART0 Special Mode Register UART1 Special Mode Register 4 UART1 Special Mode Register 3 UART1 Special Mode Register 2 UART1 Special Mode Register UART2 Special Mode Register 4 UART2 Special Mode Register 3 UART2 Special Mode Register 2 UART2 Special Mode Register UART2 Transmit/Receive Mode Register UART2 Bit Rate Generator UART2 Transmit Buffer Register UART2 Transmit/Receive Control Register 0 UART2 Transmit/Receive Control Register 1 UART2 Receive Buffer Register
U0SMR4 U0SMR3 U0SMR2 U0SMR U1SMR4 U1SMR3 U1SMR2 U1SMR U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG U2TB U2C0 U2C1 U2RB
00h 000X0X0Xb X0000000b X0000000b 00h 000X0X0Xb X0000000b X0000000b 00h 000X0X0Xb X0000000b X0000000b 00h XXh XXh XXh 00001000b 00000010b XXh XXh
NOTES: 1. The blank areas are reserved and cannot be accessed by users. X : Nothing is mapped to this bit
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M16C/30P Group Table 4.4
Address 0380h 0381h 0382h 0383h 0384h 0385h 0386h 0387h 0388h 0389h 038Ah 038Bh 038Ch 038Dh 038Eh 038Fh 0390h 0391h 0392h 0393h 0394h 0395h 0396h 0397h 0398h 0399h 039Ah 039Bh 039Ch 039Dh 039Eh 039Fh 03A0h 03A1h 03A2h 03A3h 03A4h 03A5h 03A6h 03A7h 03A8h 03A9h 03AAh 03ABh 03ACh 03ADh 03AEh 03AFh 03B0h 03B1h 03B2h 03B3h 03B4h 03B5h 03B6h 03B7h 03B8h 03B9h 03BAh 03BBh 03BCh 03BDh 03BEh 03BFh
4. Special Function Register (SFR) SFR Information (4) (1)
Register
Count Start Flag Clock Prescaler Reset Fag One-Shot Start Flag Trigger Select Register Up-Down Flag Timer A0 Register Timer A1 Register Timer A2 Register
Symbol TABSR CPSRF ONSF TRGSR UDF TA0 TA1 TA2
After Reset 000XX000b 0XXXXXXXb 00XXX000b XXXX0000b XX0XX000b (2) XXh XXh XXh XXh XXh XXh
Timer B0 Register Timer B1 Register Timer B2 Register Timer A0 Mode Register Timer A1 Mode Register Timer A2 Mode Register
TB0 TB1 TB2 TA0MR TA1MR TA2MR
XXh XXh XXh XXh XXh XXh 00h 00h 00h
Timer B0 Mode Register Timer B1 Mode Register Timer B2 Mode Register
TB0MR TB1MR TB2MR
00XX0000b 00XX0000b 00XX0000b
UART0 Transmit/Receive Mode Register UART0 Bit Rate Generator UART0 Transmit Buffer Register UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register UART1 Transmit/Receive Mode Register UART1 Bit Rate Generator UART1 Transmit Buffer Register UART1 Transmit/Receive Control Register 0 UART1 Transmit/Receive Control Register 1 UART1 Receive Buffer Register UART Transmit/Receive Control Register 2
U0MR U0BRG U0TB U0C0 U0C1 U0RB U1MR U1BRG U1TB U1C0 U1C1 U1RB UCON
00h XXh XXh XXh 00001000b 00000010b XXh XXh 00h XXh XXh XXh 00001000b 00000010b XXh XXh X0000000b
DMA0 Request Factor Select Register DMA1 Request Factor Select Register CRC Data Register CRC Input Register
DM0SL DM1SL CRCD CRCIN
00h 00h XXh XXh XXh
NOTES: 1. The blank areas are reserved and cannot be accessed by users. 2. Bit 5 in the Up-down flag is "0" by reset. However, The values in these bits when read are indeterminate. X : Nothing is mapped to this bit
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M16C/30P Group Table 4.5
Address 03C0h 03C1h 03C2h 03C3h 03C4h 03C5h 03C6h 03C7h 03C8h 03C9h 03CAh 03CBh 03CCh 03CDh 03CEh 03CFh 03D0h 03D1h 03D2h 03D3h 03D4h 03D5h 03D6h 03D7h 03D8h 03D9h 03DAh 03DBh 03DCh 03DDh 03DEh 03DFh 03E0h 03E1h 03E2h 03E3h 03E4h 03E5h 03E6h 03E7h 03E8h 03E9h 03EAh 03EBh 03ECh 03EDh 03EEh 03EFh 03F0h 03F1h 03F2h 03F3h 03F4h 03F5h 03F6h 03F7h 03F8h 03F9h 03FAh 03FBh 03FCh 03FDh 03FEh 03FFh
4. Special Function Register (SFR) SFR Information (5) (1)
Register Symbol AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh After Reset
A/D Register 0 A/D Register 1 A/D Register 2 A/D Register 3 A/D Register 4 A/D Register 5 A/D Register 6 A/D Register 7
A/D Control Register 2 A/D Control Register 0 A/D Control Register 1
ADCON2 ADCON0 ADCON1
XXX000X0b 000X0XXXb 00000XXXb
Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P2 Register Port P3 Register Port P2 Direction Register Port P3 Direction Register Port P4 Register Port P5 Register Port P4 Direction Register Port P5 Direction Register Port P6 Register Port P7 Register Port P6 Direction Register Port P7 Direction Register Port P8 Register Port P9 Register Port P8 Direction Register Port P9 Direction Register Port P10 Register Port P10 Direction Register
P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 P5 PD4 PD5 P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 PD10
XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00X00000b 00h XXh 00h
Pull-Up Control Register 0 Pull-Up Control Register 1 Pull-Up Control Register 2 Port Control Register
PUR0 PUR1 PUR2 PCR
00h 00000000b (2) 00000010b (2) 00h 00h
NOTES: 1. The blank areas are reserved and cannot be accessed by users. 2. At hardware reset, the register is as follows: * "00000000b" where "L" is inputted to the CNVSS pin * "00000010b" where "H" is inputted to the CNVSS pin At software reset, the register is as follows: * "00000000b" where the PM01 to PM00 bits in the PM0 register are "00b" (single-chip mode). * "00000010b" where the PM01 to PM00 bits in the PM0 register are "01b" (memory expansion mode) or "11b" (microprocessor mode). X : Nothing is mapped to this bit
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M16C/30P Group
5. Reset
5.
5.1
Reset
Hardware Reset
Hardware reset and software reset are available to reset the microcomputer.
The microcomputer resets pins, the CPU and SFR by setting the RESET pin. If the supply voltage meets the recommended operating conditions, the microcomputer resets all pins when an "L" signal is applied to the RESET pin (see Table 5.1 Pin Status When RESET Pin Level is "L"). The oscillation circuit is also reset and the main clock starts oscillation. The microcomputer resets the CPU and SFR when the signal applied to the RESET pin changes low ("L") to high ("H"). The microcomputer executes the program in an address indicated by the reset vector. The internal RAM is not reset. When an "L" signal is applied to the RESET pin while writing data to the internal RAM, the internal RAM is in an indeterminate state. Figure 5.1 shows an Example Reset Circuit. Figure 5.2 shows a Reset Sequence. Table 5.1 lists pin states while the RESET pin is held low ("L").
5.1.1
Reset on a Stable Supply Voltage
(1) Apply "L" to the RESET pin (2) Apply 20 or more clock cycles to the XIN pin (3) Apply an "H" signal to the RESET pin
5.1.2
(1) (2) (3) (4) (5)
Power-on Reset
Apply "L" to the RESET pin Raise the supply voltage to the recommended operating level Insert td(P-R) ms as wait time for the internal voltage to stabilize Apply 20 or more clock cycles to the XIN pin Apply "H" to the RESET pin
Recommended operating voltage VCC1 0V RESET VCC1 RESET 0.2VCC1 or below 0V Supply a clock with td(P-R) + 20 or more cycles to the XIN pin NOTES : 1. Use the M16C/30P on VCC1=VCC2. 0.2VCC1 or below
Figure 5.1
Example Reset Circuit
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M16C/30P Group
5. Reset
VCC1, VCC2 XIN td(P-R) More than 20 cycles are needed
Microprocessor mode BYTE = H RESET BCLK 28cycles
BCLK Content of reset vector Address FFFFCh FFFFDh FFFFEh
RD
WR
CS0 Microprocessor mode BYTE = L Address FFFFCh FFFFEh
Content of reset vector
RD
WR
CS0 Single chip mode Address FFFFCh FFFFEh Content of reset vector
Figure 5.2
Reset Sequence
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M16C/30P Group
5. Reset
Table 5.1
Pin Status When RESET Pin Level is "L"
Pin Name CNVSS = VSS P0 P1 P2, P3, P4_0 to P4_3 P4_4 P4_5 to P4_7 P5_0 P5_1 P5_2 P5_3 Input port Input port Input port Input port Input port Input port Input port Input port Input port
Status CNVSS = VCC1 BYTE = VSS Data input Data input Address output (undefined) CS0 output ("H" is output) Input port (Pulled high) WR output ("H" is output) BHE output (undefined) RD output ("H" is output) BCLK output BYTE = VCC1 Data input Input port Address output (undefined) CS0 output ("H" is output) Input port (Pulled high) WR output ("H" is output) BHE output (undefined) RD output ("H" is output) BCLK output
P5_4 P5_5 P5_6 P5_7
Input port Input port Input port Input port
HLDA output (The output HLDA output (The output value depends on the input to value depends on the input to the HOLD pin) the HOLD pin) HOLD input ALE output ("L" is output) RDY input Input port HOLD input ALE output ("L" is output) RDY input Input port
P6, P7, P8_0 to P8_4, P8_6, P8_7, P9, P10 Input port
NOTES: 1. Shown here is the valid pin state when the internal power supply voltage has stabilized after power on. When CNVSS = VCC1, the pin state is indeterminate until the internal power supply voltage stabilizes.
5.2
Software Reset
The microcomputer resets pins, the CPU and SFR when the PM03 bit in the PM0 register is set to "1" (microcomputer reset). Then the microcomputer executes the program in an address determined by the reset vector. Set the PM03 bit to "1" while the main clock is selected as the CPU clock and the main clock oscillation is stable. In the software reset, the microcomputer does not reset a part of the SFR. Refer to 4. Special Function Register (SFR) for details. Processor mode remains unchanged since the PM01 to PM00 bits in the PM0 register are not reset.
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5. Reset
5.3
Internal Space
Figure 5.3 shows CPU Register Status After Reset. Refer to 4. Special Function Register (SFR) for SFR states after reset.
b15
b0
0000h 0000h 0000h 0000h 0000h 0000h 0000h
Data Register(R0) Data Register(R1) Data Register(R2) Data Register(R3) Address Register(A0) Address Register(A1) Frame Base Register(FB)
b0
b19
00000h Content of addresses FFFFEh to FFFFCh
b15 b0
Interrupt Table Register(INTB) Program Counter(PC)
0000h 0000h 0000h
b15 b0
User Stack Pointer(USP) Interrupt Stack Pointer(ISP) Static Base Register(SB)
0000h
b15 b8 b7 b0
Flag Register(FLG)
IPL
UI
OB S Z DC
Figure 5.3
CPU Register Status After Reset
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5. Reset
5.4
Cold Start-up / Warm Start-up Determine Function
As for the cold start-up/warm start-up determine function, the WDC5 flag in the WDC register determines either cold start-up (reset process) when power-on or warm start-up (reset process) when reset signal is applied during the microcomputer running. Default value of the WDC5 bit is "0" (cold start-up) when power-on. It is set to "1" (warm start-up) by writing desired values to the WDC register. The WDC bit is not reset, regardless of a software reset or a reset operation. Figure 5.4 shows Cold Start-up/Warm Start-up Determine Function Block Diagram. Figure 5.5 shows the Cold Start-up/Warm Start-up Determine Function Operation Example. Figure 5.6 shows WDC Register.
WDC5 Bit Write to WDC register S Q WARM/COLD (Cold start, warm start)
Internal power on reset
R
Figure 5.4
Cold Start-up/Warm Start-up Determine Function Block Diagram
5V
VCC
0V 5V
RESET
0V
T1
Pch transistor ON (about 4V) CPU reset exited Set to "1" by program
T > 100 sec.
"1"
T2
WDC5 Flag
"0"
"1" is held even if RESET becomes 0V.
Program start
Reset Sequence (16MHz, about 20 sec.)
Becomes "0" on the rising edge of VCC
NOTES: 1. The timing of which WDC5 is set is affected by how the RESET signal rises (Time lag between T1 and T2).
Figure 5.5
Cold Start-up/Warm Start-up Determine Function Operation Example
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5. Reset
Watchdog Timer Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol Address 000Fh WDC Bit Symbol Bit Name -- High-order Bit of Watchdog Timer (b4-b0) WDC5 -- (b6) WDC7 Cold Start / Warm Start Discrimination Flag(1, 2) Reserved Bit Prescaler Select Bit
After Reset 00XXXXXXb Function
RW RO
0 : Cold Start 1 : Warm Start Set to "0" 0 : Divided by 16 1 : Divided by 128
RW RW RW
NOTES : 1. Writing to the WDC register causes the WDC5 bit to be set to "1" (w arm start). If the voltage applied to VCC1 is less than 4.0 V, either w rite to this register w hen the CPU clock frequency is 2 MHz or w rite tw ice. 2. The WDC5 bit is set to "0" (cold start) w hen pow er is turned on and can be set to "1" by program only.
Figure 5.6
WDC Register
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6. Processor Mode
6.
6.1
Processor Mode
Types of Processor Mode
Three processor modes are available to choose from: single-chip mode, memory expansion mode, and microprocessor mode. Table 6.1 shows the Features of Processor Modes. Table 6.1 Features of Processor Modes
Processor Modes Single-Chip Mode Memory Expansion Mode Microprocessor Mode
Access Space Pins which are Assigned I/O Ports All pins are I/O ports or peripheral function I/O pins SFR, Internal RAM, Internal ROM SFR, Internal RAM, Internal ROM, Some pins serve as bus control pins (1) (1) External Area SFR, Internal RAM, External Area (1) Some pins serve as bus control pins (1)
NOTES: 1. Refer to 7. Bus.
6.2
Setting Processor Modes
Processor mode is set by using the CNVSS pin and the PM01 to PM00 bits in the PM0 register. Table 6.2 shows the Processor Mode After Hardware Reset. Table 6.3 shows the PM01 to PM00 Bits Set Values and Processor Modes. Table 6.2 Processor Mode After Hardware Reset
CNVSS Pin Input Level VSS VCC1 (1)
Processor Modes Single-Chip Mode Microprocessor Mode
NOTES: 1. If the microcomputer is reset in hardware by applying VCC1 to the CNVSS pin (hardware reset), the internal ROM cannot be accessed regardless of PM01 to PM00 bits.
Table 6.3 PM01 to PM00 Bits Set Values and Processor Modes
PM01 to PM00 Bits 00b 01b 10b 11b
Processor Modes Single-Chip Mode Memory Expansion Mode Do not set Microprocessor Mode
Rewriting the PM01 to PM00 bits places the microcomputer in the corresponding processor mode regardless of whether the input level on the CNVSS pin is "H" or "L". Note, however, that the PM01 to PM00 bits cannot be rewritten to "01b" (memory expansion mode) or "11b" (microprocessor mode) at the same time the PM07 to PM02 bits are rewritten. Note also that these bits cannot be rewritten to enter microprocessor mode in the internal ROM, nor can they be rewritten to exit microprocessor mode in areas overlapping the internal ROM. If the microcomputer is reset in hardware by applying VCC1 to the CNVSS pin (hardware reset 1 or brown-out detection reset (hardware reset 2)), the internal ROM cannot be accessed regardless of PM01 to PM00 bits. Figures 6.1 and 6.2 show the PM0 Register and PM1 Register (1). Figure 6.4 show the Memory Map in Single Chip Mode.
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6. Processor Mode
Processor Mode Register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol PM0 Bit Symbol PM00
Address 0004h Bit Name Processor Mode Bit
(2)
After Reset (3) 00000000b (CNVSS pin = L) 00000011b (CNVSS pin = H) Function
b1 b0
RW RW
PM01 R/W Mode Select Bit (3) Softw are Reset Bit Reserved Bit Reserved Bit Port P4_0 to P4_3 Function Select Bit (3) BCLK Output Disable Bit (3)
0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Do not set 1 1 : Microprocessor mode
___ _____ ____
RW
PM02 PM03 -- (b4) -- (b5) PM06 PM07
0 : RD, BHE, WR ___ ______ _____ 1 : RD, WRH, WRL Setting this bit to "1" resets the microcomputer. When read, its content is "0". Set to "0". Set to "0". 0 : Address output 1 : Port function (Address is not output) 0 : BCLK is output 1 : BCLK is not output (Pin is left high-impedance)
RW RW RW RW RW RW
NOTES : 1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (w rite enable). 2 The PM01 to PM00 bits do not change at softw are reset. 3 Effective w hen the PM01 to PM00 bits are set to "01b" (memory expansion mode) or "11b" (microprocessor mode).
Figure 6.1
PM0 Register
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6. Processor Mode
Processor Mode Register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol PM1 Bit Symbol PM10 -- (b1) -- (b2) -- (b3) -- (b4) -- (b5) -- (b6) PM17
Address 0005h Bit Name CS2 Area Sw itch Bit (Data Block Enable Bit)
(2)
After Reset 00XXX0X0b Function 0 : 08000h to 26FFFh (Block A disable) 1 : 10000h to 26FFFh (Block A enable) RW RW -- RW -- -- -- RW RW
Nothing is assigned. When w rite, set to "0". When read, its content is indeterminate. Reserved Bit Set to "0".
Nothing is assigned. When w rite, set to "0". When read, its content is indeterminate. Nothing is assigned. When w rite, set to "0". When read, its content is indeterminate. Nothing is assigned. When w rite, set to "0". When read, its content is indeterminate. Reserved Bit Wait Bit
(3)
Set to "0". 0 : No w ait state 1 : With w ait state (1 w ait)
NOTES : 1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (w rite enable). 2. Set the PM10 bit to "0" for Mask ROM version and one time flash version. For flash memory version, the PM10 bit controls w hether Block A is enabled or disabled. When the PM10 bit is set to "1", 0F000h to 0FFFFh can be used as internal ROM area. In addition, for the flash memory version and one time flash version, the PM10 bit is automatically set to "1" w hile the FMR01 bit in the FMR0 register is set to "1" (CPU rew rite mode or the FMSTP bit enabled). 3. When PM17 bit is set to "1" (w ith w ait state), one w ait state is inserted w hen accessing the internal RAM, or internal ROM. When PM17 bit is set to "1" and accesses an external area, set the CSiW bit in the CSR register (i=0 to 3) to "0" (w ith w ait state).
Figure 6.2
PM1 Register (1)
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6. Processor Mode
Processor Mode Register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol PM1 Bit Symbol PM10 -- (b1) -- (b2) PM13 -- (b4) -- (b5) -- (b6) PM17
Address 0005h Bit Name CS2 Area Sw itch Bit (2)
After Reset 00XXX0X0b Function 0 : 08000h to 26FFFh 1 : 10000h to 26FFFh RW RW -- RW RW -- -- RW RW
Nothing is assigned. When w rite, set to "0". When read, its content is indeterminate. Reserved Bit Internal Reserved Area Expansion Bit (4) Set to "0". (NOTE 5)
Nothing is assigned. When w rite, set to "0". When read, its content is indeterminate. Nothing is assigned. When w rite, set to "0". When read, its content is indeterminate. Reserved Bit Wait Bit (3) Set to "0". 0 : No w ait state 1 : With w ait state (1 w ait)
NOTES : 1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (w rite enable). 2. Set the PM10 bit to "0" for one time flash version. 3. When PM17 bit is set to "1" (w ith w ait state), one w ait state is inserted w hen accessing the internal RAM, or internal ROM. When PM17 bit is set to "1" and accesses an external area, set the CSiW bit in the CSR register (i=0 to 3) to "0" (w ith 4. The PM13 bit is automatically set to "1" w hen the FMR01 bit in the FMR0 register is "1" (CPU rew rite mode). 5. The access area is changed by the PM13 bit as listed in the table below . Access Area PM13=0 PM13=1 RAM Up to Addresses 00400h to 03FFFh (15 Kbytes The entire area is usable Internal ROM Up to Addresses D0000h to FFFFFh (192 KbyteThe entire area is usable External Address 04000h to 07FFFh are usable Address 80000h to CFFFFh are usable Address 04000h to 07FFFh are reserved Address 80000h to CFFFFh are reserved (Memory expansion mode)
Figure 6.3
PM1 Register (2) (M30304GDPFP, M30304GDPGP, M30304GEPFP, M30304GEPGP, M30302GGPFP, M30302GGPGP)
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6. Processor Mode
Single-Chip Mode
00000h SFR 00400h Internal RAM XXXXXh
PM13=0 or without PM13 bit
Internal RAM Size 5 Kbytes 6 Kbytes 12 Kbytes Address XXXXXh 017FFh 01BFFh 033FFh Size 96 Kbytes 128 Kbytes 160 Kbytes 192 Kbytes 256 Kbytes Internal ROM Address YYYYYh E8000h E0000h D8000h D0000h D0000h(2)
PM13=1
Can not use Internal RAM Internal ROM Size Address XXXXXh Size Address YYYYYh 12 Kbytes 033FFh 160 Kbytes D8000h 192 Kbytes YYYYYh Internal ROM FFFFFh NOTE : 1. For the mask ROM version and one time flash version set the PM10 bit to "0" (08000h to 26FFFh for CS2 area). 2. 192-Kbyte internal ROM space is available for use. 256 Kbytes D0000h C0000h
Figure 6.4
Memory Map in Single Chip Mode
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7. Bus
7.
Bus
During memory expansion or microprocessor mode, some pins serve as the bus control pins to perform data input/ output to and from external devices. These bus control pins include A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/ WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK.
7.1
Bus Mode
The bus mode is the "separate bus mode" that separates data and address.
7.2
Bus Control
The following describes the signals needed for accessing external devices and the functionality of software wait.
7.2.1
Address Bus
The address bus consists of 20 lines, A0 to A19. The address bus width can be chosen to be 16 or 20 bits by using the PM06 bit in the PM0 register. Table 7.1 shows the PM06 Bit Set Value and Address Bus Width. Table 7.1 PM06 Bit Set Value and Address Bus Width Set Value (1) Pin Function Address Bus Width PM06=1 P4_0 to P4_3 16 bits
PM06=0
A16 to A19
20 bits
NOTES: 1. No values other than those shown above can be set.
When processor mode is changed from single-chip mode to memory extension mode, the address bus is indeterminate until any external area is accessed.
7.2.2
Data Bus
When input on the BYTE pin is high (data bus is 8 bits wide), 8 lines D0 to D7 comprise the data bus; when input on the BYTE pin is low(data bus is 16 bits wide), 16 lines D0 to D15 comprise the data bus. Do not change the input level on the BYTE pin while in operation.
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7. Bus
7.2.3
Chip Select Signal
The chip select (hereafter referred to as the CS) signals are output from the CSi (i = 0 to 3) pins. These pins can be chosen to function as I/O ports or as CS by using the CS bit in the CSR register. Figure 7.1 shows the CSR Register. During 1-Mbyte mode, the external area can be separated into up to 4 by the CSi signal which is output from the CSi pin. Figure 7.2 shows the Example of Address Bus and CSi Signal Output in 1-Mbyte mode.
Chip Select Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address 0008h CSR Bit Name Bit Symbol ____ CS0 Output Enable Bit CS0
____
CS1 CS2 CS3 CS0W CS1W CS2W CS3W NOTES :
_____
CS1 Output Enable Bit
____
After Reset 01h Function 0 : Chip select output disabled (f unctions as I/O port) 1 : Chip select output enabled
RW RW RW RW RW
CS2 Output Enable Bit
____
CS3 Output Enable Bit
____
CS0 Wait Bit
____
0 : With w ait state (1 w ait) 1 : Without w ait state (1, 2)
RW RW RW RW
CS1 Wait Bit
____
CS2 Wait Bit
____
CS3 Wait Bit
____
1. Where the RDY signal is used in the area indicated by CSi (i = 0 to 3) or the multiplex bus is used, set the CSiW bit to "0" (w ith w ait state). 2. If the PM17 bit in the PM1 register is set to "1" (w ith w ait state), set the CSiW bit to "0" (w ith w ait state).
Figure 7.1
CSR Register
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7. Bus
Example 1 To access the external area indicated by CSj in the next cycle after accessing the external area indicated by CSi The address bus and the chip select signal both change state between these two cycles.
Example 2 To access the internal ROM or internal RAM in the next cycle after accessing the external area indicated by CSi The chip select signal changes state but the address bus does not change state
Access to the external area indicated by CSi
Access to the external area indicated by CSj
Access to the external Access to the internal area indicated by CSi ROM or internal RAM
BCLK Read signal Data bus Address bus CSi CSj Data Data
BCLK Read signal Data bus Address bus CSi Data Address
Address Address
Example 3 To access the external area indicated by CSi in the next cycle after accessing the external area indicated by the same CSi The address bus changes state but the chip select signal does not change state
Example 4
Not to access any area (nor instruction prefetch generated) in the next cycle after accessing the external area indicated by CSi Neither the address bus nor the chip select signal changes state between these two cycles
Access to the external area indicated by CSi
Access to the same external area
Access to the external area indicated by CSi
No access
BCLK Read signal Data bus Address bus CSi Data Data
BCLK Read signal Data bus Address bus CSi Data Address
Address Address
NOTES : 1. These examples show the address bus and chip select signal when accessing areas in two successive cycles. The chip select bus cycle may be extended more than two cycles depending on a combination of these examples.
Shown above is the case where separate bus is selected and the area is accessed for read without wait states. i = 0 to 3, j = 0 to 3 (not including i, however)
Figure 7.2
Example of Address Bus and CSi Signal Output in 1-Mbyte mode
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7. Bus
7.2.4
Read and Write Signals
When the data bus is 16 bits wide, the read and write signals can be chosen to be a combination of RD, BHE and WR or a combination of RD, WRL and WRH by using the PM02 bit in the PM0 register. When the data bus is 8 bits wide, use a combination of RD, WR and BHE. Table 7.2 shows the Operation of RD, WRL, and WRH Signals. Table 7.3 shows the Operation of RD, WRL, and BHE Signals. Table 7.2 Operation of RD, WRL and WRH Signals
Data Bus Width 16-bit (BYTE pin input = L)
RD L H H H
WRL H L H L
WRH H H L L
Status of External Data Bus Read data Write 1 byte of data to an even address Write 1 byte of data to an odd address Write data to both even and odd addresses
Table 7.3
Operation of RD, WRL and BHE Signals
Data Bus Width 16-bit (BYTE pin input = L)
8-bit (BYTE pin input = H)
RD H L H L H L H L
WRL L H L H L H L H
BHE L L H H L L Not used Not used
A0 H H L L L L H or L H or L
Status of External Data Bus Write 1 byte of data to an odd address Read 1 byte of data from an odd address Write 1 byte of data to an even address Read 1 byte of data from an even address Write data to both even and odd addresses Read data from both even and odd addresses Write 1 byte of data Read 1 byte of data
7.2.5
ALE Signal
The ALE signal latches the address.
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7. Bus
7.2.6
RDY Signal
This signal is provided for accessing external devices which need to be accessed at low speed. If input on the RDY pin is asserted low at the last falling edge of BCLK of the bus cycle, one wait state is inserted in the bus cycle. While in a wait state, the following signals retain the state in which they were when the RDY signal was acknowledged. A0 to A19, D0 to D15, CS0 to CS3, RD, WRL, WRH, WR, BHE, ALE, HLDA Then, when the input on the RDY pin is detected high at the falling edge of BCLK, the remaining bus cycle is executed. Figure 7.3 shows Example in which the Wait State was Inserted into Read Cycle by RDY Signal. To use the RDY signal, set the corresponding bit (CS3W to CS0W bits) in the CSR register to "0" (with wait state). When not using the RDY signal, the RDY pin must be pulled-up.
In an instance of separate bus
BCLK
RD CSi
(i=0 to 3)
RDY
tsu(RDY - BCLK)
Accept timing of RDY signal
: Wait using RDY signal : Wait using software
tsu (RDY-BCLK) : RDY Input Setup Time
Figure 7.3
Example in which Wait State was Inserted into Read Cycle by RDY Signal
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7. Bus
7.2.7
HOLD Signal
This signal is used to transfer control of the bus from the CPU or DMAC to an external circuit. When the input on HOLD pin is pulled low, the microcomputer is placed in a hold state after the bus access then in process finishes. The microcomputer remains in the hold state while the HOLD pin is held low, during which time the HLDA pin outputs a low-level signal. Table 7.4 shows the Microcomputer Status in Hold State. Bus-using priorities are given to HOLD, DMAC, and CPU in order of decreasing precedence. However, if the CPU is accessing an odd address in word units, the DMAC cannot gain control of the bus during two separate accesses.
HOLD > DMAC > CPU
Figure 7.4 Bus-Using Priorities
Table 7.4
Microcomputer Status in Hold State
Item BCLK A0 to A19, D0 to D15, CS0 to CS3, RD, WRL,WRH, WR, BHE I/O ports HLDA Internal Peripheral Circuits ALE Signal NOTES: 1. When I/O port function is selected. P6 to P10 Output High-impedance
Status
P0, P1, P3, P4 (1) High-impedance Maintains status when HOLD signal is received Output "L" ON (but watchdog timer stops) Undefined
7.2.8
BCLK Output
If the PM07 bit in the PM0 register is set to "0" (output enable), a clock with the same frequency as that of the CPU clock is output as BCLK from the BCLK pin. Refer to 9.2 CPU Clock and Peripheral Function Clock.
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7. Bus
Table 7.5
Pin Functions for Each Processor Mode
Memory Expansion Mode or Microprocessor Mode 8 bits 16 bits "H" "L" D0 to D7 D0 to D7 I/O ports D8 to D15 A0 A0 A1 to A7 A1 to A7 A8 A8 A9 to A15 A16 to A19 I/O ports I/O ports CS0 I/O ports CS1 I/O ports CS2 I/O ports CS3 WR - (1) BHE - (1) RD BCLK HLDA HOLD ALE RDY WRH WRL
Processor Mode Data Bus Width BYTE Pin P0_0 to P0_7 P1_0 to P1_7 P2_0 P2_1 to P2_7 P3_0 P3_1 to P3_7 P4_0 to P4_3 P4_4 P4_5 P4_6 P4_7 P5_0 P5_1 P5_2 P5_3 P5_4 P5_5 P5_6 P5_7
PM06=0 PM06=1 CS0=0 CS0=1 CS1=0 CS1=1 CS2=0 CS2=1 CS3=0 CS3=1 PM02=0 PM02=1 PM02=0 PM02=1
I/O ports : Function as I/O ports or peripheral function I/O pins.
NOTES: 1. If the data bus is 8 bits wide, make sure the PM02 bit is set to "0" (RD, BHE, WR).
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7. Bus
7.2.9
External Bus Status When Internal Area Accessed
Table 7.6 shows the External Bus Status When Internal Area Accessed. Table 7.6 External Bus Status When Internal Area Accessed
Item A0 to A19 D0 to D15 When Read When Write
SFR Accessed Address output High-impedance Output data RD, WR, WRL, WRH output BHE output Output "H" Output "L"
RD, WR, WRL, WRH BHE CS0 to CS3 ALE
Internal ROM, RAM Accessed Maintain status before accessed address of external area or SFR High-impedance Undefined Output "H" Maintain status before accessed status of external area or SFR Output "H" Output "L"
7.2.10
Software Wait
Software wait states can be inserted by using the PM17 bit in the PM1 register, the CS0W to CS3W bits in the CSR register, and the CSE register. The SFR area is unaffected by these control bits. This area is always accessed in 2 BCLK or 3 BCLK cycles as determined by the PM20 bit in the PM2 register. See Table 7.7 Bit and Bus Cycle Related to Software Wait for details. To use the RDY signal, set the corresponding CS3W to CS0W bit to "0" (with wait state). Table 7.7 shows the Bit and Bus Cycle Related to Software Wait. Figure 7.5 shows the Typical Bus Timings Using Software Wait.
Table 7.7
Bit and Bus Cycle Related to Software Wait
PM1 Register PM17 Bit (3) 0 1 0 CSR Register CS3W Bit (1) CS2W Bit (1) CS1W Bit (1) CS0W Bit (1) - - 1
Area
Software Wait
Bus Cycle
Internal RAM, ROM External Area
No wait 1 wait No wait
- 1
0 0
1 wait 1 wait
1 BCLK cycle (2) 2 BCLK cycles 1 BCLK cycle (read) 2 BCLK cycles (write) 2 BCLK cycle (2) 2 BCLK cycle
NOTES: 1. To use the RDY signal, set this bit to "0" (with wait state). 2. After reset, the PM17 bit is set to "0" (without wait state), all of the CS0W to CS3W bits are set to "0" (with wait state). Therefore, the internal RAM and internal ROM are accessed with no wait states, and all external areas are accessed with one wait state. 3. When PM17 bit is set to "1" and accesses an external area, set the CSiW (i=0 to 3) bits to "0" (with wait state).
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7. Bus
(1) Separate Bus, No Wait Setting Bus cycle (1) Bus cycle (1)
BCLK Write signal Read signal Data bus Address bus CS
Output
Input
Address
Address
(2) Separate Bus, 1-Wait Setting Bus cycle (1) BCLK Write signal Read signal Data bus Address bus CS
Output
Input
Bus cycle (1)
Address
Address
NOTES : 1. These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and write cycles in succession.
Figure 7.5
Typical Bus Timings Using Software Wait
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8. Memory Space Expansion Function
8.
Memory Space Expansion Function
The following describes a memory space extension function. During memory expansion or microprocessor mode, the memory space expansion function allows the access space to be expanded using the appropriate register bits.
8.1
1-Mbyte Mode
In this mode, the memory space is 1 Mbyte. In 1-Mbyte mode, the external area to be accessed is specified using the CSi (i = 0 to 3) signals (hereafter referred to as the CSi area). Figure 8.1 and 8.2 show Memory Map and CS area. Refer to Figure 8.1 for models without the PM13 bit. See Figure 6.2 PM1 Register (1) and Figure 6.3 PM1 Register (2) to check presence or absence of the PM13 bit.
Memory expansion mode 00000h 00400h SFR Internal RAM Reserved area 04000h 08000h 10000h 27000h 28000h 30000h Reserved area Reserved, External area (1)
Microprocessor mode SFR Internal RAM Reserved area
CS3
Reserved, External area (1) Reserved area
(16 Kbytes)
CS2 (PM10=0 : 124 Kbytes) CS2 (PM10=1 : 92 Kbytes) CS1 (32 Kbytes)
External area
External area
CS0 (Memory expansion mode:640 Kbytes )
D0000h
Reserved area Internal ROM
CS0 (Microprocessor mode:832 Kbytes)
FFFFFh
PM13=0 Internal RAM Size 5 Kbytes 6 Kbytes 12 Kbytes Address XXXXXh 017FFh 01BFFh 033FFh Size 96 Kbytes 128 Kbytes 160 Kbytes 192 Kbytes 256 Kbytes Internal ROM Address YYYYYh E8000h E0000h D8000h D0000h D0000h(2) CS0 Memory expansion mode 30000h to CFFFFh Microprocessor mode 30000h to FFFFFh External Area CS1 28000h to 2FFFFh CS2 When PM10=0 08000h to 26FFFh When PM10=1 10000h to 26FFFh CS3 04000h to 07FFFh
NOTES : 1. For flash memory version, when the PM10 bit in the PM1 register is set to "1", 0F000h to 0FFFFh can be used as internal ROM area. For mask ROM version and one-time flash version, set the PM10 bit to "0" (08000h to 26FFFh for CS area). 2. 192-Kbyte internal ROM space is available for use.
Figure 8.1
Memory Mapping and CS Area in 1-Mbyte mode (PM13=0)
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8. Memory Space Expansion Function
Memory expansion mode 00000h 00400h Internal RAM XXXXXh Reserved area 08000h 10000h 27000h 28000h 30000h Reserved area Reserved, External area
(1)
Microprocessor mode SFR Internal RAM Reserved area Reserved, External area (1) Reserved area
SFR
CS2 (PM10=0 : 124 Kbytes) CS2 (PM10=1 : 92 Kbytes) CS1 (32 Kbytes)
External area
External area
CS0 (Memory expansion mode:640 Kbytes )
80000h YYYYYh Internal ROM FFFFFh
Reserved area
CS0 (Microprocessor mode:832 Kbytes)
PM13=1 Internal RAM Internal ROM External Area CS1 28000h to 2FFFFh CS2 When PM10=0 08000h to 26FFFh When PM10=1 10000h to 26FFFh CS3 No area Size Address XXXXXh Size Address YYYYYh CS0 Memory expansion mode 12 Kbytes 033FFh 160 Kbytes D8000h 30000h to 7FFFFh 192 Kbytes D0000h Microprocessor mode 30000h to FFFFFh 256 Kbytes C0000h
NOTE : 1. For flash memory version, when the PM10 bit in the PM1 register is set to "1", 0F000h to 0FFFFh can be used as internal ROM area.
Figure 8.2
Memory Mapping and CS Area in 1-Mbyte mode (PM13=1)
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9. Clock Generating Circuit
9.
9.1
Clock Generating Circuit
Types of the Clock Generating Circuit
Two circuits are incorporated to generate the system clock signal : * Main clock oscillation circuit * Sub clock oscillation circuit Table 9.1 lists the Clock Generation Circuit Specifications. Figure 9.1 shows the clock generation circuit. Figures 9.2 to 9.4 show the clock-related registers. Table 9.1 Clock Generation Circuit Specifications
Item Use of Clock Clock Frequency Usable Oscillator Pins to Connect Oscillator Oscillation Stop, Restart Function Oscillator Status After Reset Other
Main Clock Oscillation Circuit * CPU clock source * Peripheral function clock source 0 to 16 MHz * Ceramic oscillator * Crystal oscillator XIN, XOUT Presence Oscillating Externally derived clock can be input
Sub Clock Oscillation Circuit * CPU clock source * Timer A, B's clock source 32.768 kHz * Crystal oscillator XCIN, XCOUT Presence Stopped
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Sub clock generating circuit XCIN CM04 Sub clock XCOUT
I/O ports
CM01_CM00=00b PM01_PM00=00b, CM01_CM00=01b PM01_PM00=00b, CM01_CM00=10b 1/32
f1 fC32
CLKOUT PM01_PM00=00b, CM01_CM00=11b
PCLK0=1
f2
PCLK0=0
fC f8 f32
fAD
f1SIO
PCLK1=1
f2SIO
PCLK1=0 CM10=1(stop mode) SQ XIN R XOUT Main clock f8SIO f32SIO
ebc a
Main clock generating circuit CM05 CM02 Divider
d
fC
CM07=0 CPU clock BCLK CM07=1
S WAIT instruction R
Q
e a
RESET Software reset NMI Interrupt request level judgment output
b
1/2 1/2 1/4 1/8 1/2 1/16 1/2
c
1/32
1/2 1/2
CM06=0 CM17_CM16=11b CM06=0 CM17_CM16=10b CM06=1
d
CM02, CM04, CM05, CM06, CM07: Bits in CM0 register CM10, CM16, CM17: Bits in CM1 register PCLK0, PCLK1: Bits in PCLKR register
CM06=0 CM17_CM16=01b CM06=0 CM17_CM16=00b
Details of divider
Figure 9.1
Clock Generation Circuit
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System Clock Control Register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol CM0 Bit Symbol CM00
Address 0006h Bit Name Clock Output Function Select Bit (Valid only in singlechip mode)
b1 b0
After Reset 01001000b Function 0 0 : I/O port P5_7 0 1 : fC output 1 0 : f8 output 1 1 : f32 output RW RW
CM01
RW
CM02 CM03 CM04 CM05 CM06 CM07
WAIT Mode Peripheral 0 : Do not stop peripheral function clock in w ait mode Function Clock Stop Bit 1 : Stop peripheral function clock in w ait mode (8) XCIN-XCOUT Drive Capacity Select Bit (2) Port XC Select Bit (2) Main Clock Stop Bit
(3, 10, 11)
RW RW RW RW RW RW
0 : LOW 1 : HIGH 0 : I/O port P8_6, P8_7 1 : XCIN-XCOUT generation function (9) 0 : On 1 : Off
(4, 5)
Main Clock Division Select Bit 0 (7, 11)
0 : CM16 and CM17 valid 1 : Division by 8 mode
System Clock Select Bit 0 : Main clock (6, 10) 1 : Sub-clock
NOTES : 1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (w rite enable). 2. The CM03 bit is set to "1" (high) w hile the CM04 bit is set to "0," or w hen entered to stop mode. 3. This bit is provided to stop the main clock w hen the low pow er dissipation mode is selected. This bit cannot be used for detection as to w hether the main clock stopped or not. To stop the main clock, set bits in the follow ing order. (a) Set the CM07 bit to "1" (Sub-clock select) w ith the sub-clock stably oscillating. (b) Set the CM05 bit to "1" (Stop). 4. During external clock input, Set the CM05 bit to "0" (oscillate). 5. When CM05 bit is set to "1", the XOUT pin goes "H". Furthermore, because the internal feedback resistor remains connected, the XIN pin is pulled "H" to the same level as XOUT via the feedback resistor. 6. After setting the CM04 bit to "1" (XCIN-XCOUT oscillator function), w ait until the sub-clock oscillates stably before sw itching the CM07 bit from "0" to "1" (sub-clock). 7. When entering stop mode from high or middle speed mode, the CM06 bit is set to "1" (divide-by-8 mode). 8. The fC32 clock does not stop. During low speed or low pow er dissipation mode, do not set this bit to "1" (peripheral clock turned off w hen in w ait mode). 9. To use a sub-clock, set this bit to "1". Also make sure ports P8_6 and P8_7 are directed for input, w ith no pull-ups. 10. To use the main clock as the clock source for the CPU clock, set bits in the follow ing order. (a) Set the CM05 bit to "0" (oscillate). (b) Wait the main clock oscillation stabilizes. (c) Set the CM07 bit to "0". 11. When the CM05 bit = 1 (main clock turned off), the CM06 bit is fixed to "1" (divide-by-8 mode) and the CM15 bit is fixed to "1" drive capability High).
Figure 9.2
CM0 Register
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System Clock Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
0000
Symbol CM1 Bit Symbol CM10 -- (b4-b1) CM15 CM16
Address 0007h Bit Name All Clock Stop Control Bit (4) Reserved Bit XIN-XOUT Drive Capacity Select Bit(2) Main Clock Division Select Bit 1(3)
After Reset 00100000b Function 0 : Clock on 1 : All clocks off (stop mode) Set to "0" 0 : LOW 1 : HIGH
b7 b6
RW RW RW RW RW
CM17
0 0 : No division mode 0 1 : Division by 2 mode 1 0 : Division by 4 mode 1 1 : Division by 16 mode
RW
NOTES : 1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (w rite enable). 2. When entering stop mode from high or middle speed mode, or w hen the CM05 bit is set to "1" (main clock turned off) in low speed mode, the CM15 bit is set to "1" (drive capability high). 3. Effective w hen the CM06 bit is "0" (CM16 and CM17 bits enable). 4. If the CM10 bit is "1" (stop mode), XOUT goes "H" and the internal feedback resistor is disconnected. The XCIN and XCOUT pins are placed in the high-impedance state.
Figure 9.3
CM1 Register
Peripheral Clock Select Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
000000
Symbol PCLKR Bit Symbol PCLK0 PCLK1 -- (b7-b2)
Address 025Eh Bit Name Timers A, B Clock Select Bit (Clock source for the timers A and B) SI/O Clock Select Bit (Clock source for UART0 to UART2) Reserved bit 0 : f2 1 : f1
After Reset 00000011b Function RW RW RW RW
0 : f2SIO 1 : f1SIO Set to "0"
NOTES : 1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (w rite enable).
Figure 9.4
PCLKR Register
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The following describes the clocks generated by the clock generation circuit.
9. Clock Generating Circuit
9.1.1
Main Clock
This clock is used as the clock source for the CPU and peripheral function clocks. This clock is used as the clock source for the CPU and peripheral function clocks. The main clock oscillator circuit is configured by connecting a resonator between the XIN and XOUT pins. The main clock oscillator circuit contains a feedback resistor, which is disconnected from the oscillator circuit during stop mode in order to reduce the amount of power consumed in the chip. The main clock oscillator circuit may also be configured by feeding an externally generated clock to the XIN pin. Figure 9.5 shows the examples of main clock connection circuit. After reset, the main clock divided by 8 is selected for the CPU clock. The power consumption in the chip can be reduced by setting the CM05 bit in the CM0 register to "1" (main clock oscillator circuit turned off) after switching the clock source for the CPU clock to a sub clock or on-chip oscillator clock. In this case, XOUT goes "H". Furthermore, because the internal feedback resistor remains on, XIN is pulled "H" to XOUT via the feedback resistor. Note that if an externally generated clock is fed into the XIN pin, the main clock cannot be turned off by setting the CM05 bit to "1" unless the sub clock is chosen as a CPU clock. If necessary, use an external circuit to turn off the clock. During stop mode, all clocks including the main clock are turned off. Refer to 9.4 Power Control.
Microcomputer
(Built-in Feedback Resistor) CIN XIN Oscillator XOUT Rd(1) VSS COUT
Microcomputer
(Built-in Feedback Resistor) XIN
External clock
VCC1 VSS
XOUT Open
NOTES : 1. Place a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by each oscillator the oscillator manufacturer. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, place a feedback resistor between XIN and XOUT if the oscillator manufacturer recommends placing the resistor externally.
Figure 9.5
Examples of Main Clock Connection Circuit
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9. Clock Generating Circuit
9.1.2
Sub Clock
The sub clock is generated by the sub clock oscillation circuit. This clock is used as the clock source for the CPU clock, as well as the timer A and timer B count sources. In addition, an fc clock with the same frequency as that of the sub clock can be output from the CLKOUT pin. The sub clock oscillator circuit is configured by connecting a crystal resonator between the XCIN and XCOUT pins. The sub clock oscillator circuit contains a feedback resistor, which is disconnected from the oscillator circuit during stop mode in order to reduce the amount of power consumed in the chip. The sub clock oscillator circuit may also be configured by feeding an externally generated clock to the XCIN pin. Figure 9.6 shows the examples of sub clock connection circuit. After reset, the sub clock is turned off. At this time, the feedback resistor is disconnected from the oscillator circuit. To use the sub clock for the CPU clock, set the CM07 bit in the CM0 register to "1" (sub clock) after the sub clock becomes oscillating stably. During stop mode, all clocks including the sub clock are turned off. Refer to 9.4 Power Control.
Microcomputer
(Built-in Feedback Resistor) CCIN XCIN Oscillator XCOUT RCd(1) VSS CCOUT
Microcomputer
(Built-in Feedback Resistor) XCIN
External clock
VCC1 VSS
XCOUT Open
NOTES : 1. Place a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by each oscillator the oscillator manufacturer. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, place a feedback resistor between XCIN and XCOUT if the oscillator manufacturer recommends placing the resistor externally.
Figure 9.6
Examples of Sub Clock Connection Circuit
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9. Clock Generating Circuit
9.2
CPU Clock and Peripheral Function Clock
Two type clocks: CPU clock to operate the CPU and peripheral function clocks to operate the peripheral functions.
9.2.1
CPU Clock and BCLK
These are operating clocks for the CPU and watchdog timer. The clock source for the CPU clock can be chosen to be the main clock or sub clock. If the main clock is selected as the clock source for the CPU clock, the selected clock source can be divided by 1 (undivided), 2, 4, 8 or 16 to produce the CPU clock. Use the CM06 bit in CM0 register and the CM17 to CM16 bits in the CM1 register to select the divide-by-n value. After reset, the main clock divided by 8 provides the CPU clock. Note that when entering stop mode from high or middle speed mode, or when the CM05 bit in the CM0 register is set to "1" (main clock turned off) in low-speed mode, the CM06 bit in the CM0 register is set to "1" (divideby-8 mode).
9.2.2
Peripheral Function Clock (f1, f2, f8, f32, f1SIO, f2SIO, f8SIO, f32SIO, fAD, fC32)
These are operating clocks for the peripheral functions. Of these, fi (i = 1, 2, 8, 32) and fiSIO are derived from the main clock by dividing them by i. The clock fi is used for timers A and B, and fiSIO is used for serial interface. The f8 and f32 clocks can be output from the CLKOUT pin. The fAD clock is produced from the main clock, and is used for the A/D converter. When the WAIT instruction is executed after setting the CM02 bit in the CM0 register to "1" (peripheral function clock turned off during wait mode), or when the microcomputer is in low power dissipation mode, the fi, fiSIO and fAD clocks are turned off. The fC32 clock is produced from the sub clock, and is used for timers A and B. This clock can be used when the sub clock is on.
9.3
Clock Output Function
During single-chip mode, the f8, f32 or fC clock can be output from the CLKOUT pin. Use the CM01 to CM00 bits in the CM0 register to select.
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9.4
Power Control
Normal operation mode, wait mode and stop mode are provided as the power consumption control. All mode states, except wait mode and stop mode, are called normal operation mode in this document.
9.4.1
Normal Operation Mode
Normal operation mode is further classified into 4 modes. In normal operation mode, because the CPU clock and the peripheral function clocks both are on, the CPU and the peripheral functions are operating. Power control is exercised by controlling the CPU clock frequency. The higher the CPU clock frequency, the greater the processing capability. The lower the CPU clock frequency, the smaller the power consumption in the chip. If the unnecessary oscillator circuits are turned off, the power consumption is further reduced. Before the clock sources for the CPU clock can be switched over, the new clock source to which switched must be oscillating stably. If the new clock source is the main clock or sub clock, allow a sufficient wait time in a program until it becomes oscillating stably.
9.4.1.1
High-speed Mode
The main clock divided by 1 provides the CPU clock. If the sub clock is on, fC32 can be used as the count source for timers A and B.
9.4.1.2
Medium-speed Mode
The main clock divided by 2, 4, 8 or 16 provides the CPU clock. If the sub clock is on, fC32 can be used as the count source for timers A and B.
9.4.1.3
Low-speed Mode
The sub clock provides the CPU clock. The fC32 clock can be used as the count source for timers A and B.
9.4.1.4
Low Power Dissipation Mode
In this mode, the main clock is turned off after being placed in low speed mode. The sub clock provides the CPU clock. The fC32 clock can be used as the count source for timers A and B. Simultaneously when this mode is selected, the CM06 bit becomes "1" (divided by 8 mode). In the low power dissipation mode, do not change the CM06 bit. Consequently, the medium speed (divided by 8) mode is to be selected when the main clock is operated next. Table 9.2 Setting Clock Related Bit and Modes
Modes High-Speed Mode Mediumdivided by 2 Speed Mode divided by 4 divided by 8 divided by 16 Low-Speed Mode Low Power Dissipation Mode
CM1 Register CM17, CM16 00b 01b 10b - 11b - -
CM07 0 0 0 0 0 1 1
CM0 Register CM06 CM05 0 0 0 0 0 0 1 0 0 0 - 0 (1) 1 1(1)
CM04 - - - - - 1 1
- : "0" or "1" NOTES: 1. When the CM05 bit is set to "1" (main clock turned off) in low-speed mode, the mode goes to low power dissipation mode and CM06 bit is set to "1" (divided by 8 mode) simultaneously.
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9.4.2
Wait Mode
In wait mode, the CPU clock is turned off, so are the CPU (because operated by the CPU clock) and the watchdog timer. Because the main clock and sub clock all are on, the peripheral functions using these clocks keep operating.
9.4.2.1
Peripheral Function Clock Stop Function
If the CM02 bit in the CM0 register is "1" (peripheral function clocks turned off during wait mode), the f1, f2, f8, f32, f1SIO, f8SIO, f32SIO and fAD clocks are turned off when in wait mode, with the power consumption reduced that much. However, fC32 remains on.
9.4.2.2
Entering Wait Mode
The microcomputer is placed into wait mode by executing the WAIT instruction.
9.4.2.3
Pin Status During Wait Mode
Table 9.3 lists Pin Status During Wait Mode. Table 9.3 Pin Status During Wait Mode
Pin A0 to A19, D0 to D15, CS0 to CS3, BHE RD, WR, WRL, WRH HLDA, BCLK ALE I/O ports CLKOUT
Memory Expansion Mode Single-Chip Mode Microprocessor Mode Retains status before wait mode Does not become a bus control pin "H" "H" "L" Retains status before wait mode Retains status before wait mode Does not become a CLKOUT pin Does not stop Does not stop when the CM02 bit is "0". When the CM02 bit is "1", the status immediately prior to entering wait mode is maintained.
When fC selected When f8, f32 selected
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9.4.2.4
Exiting Wait Mode
The microcomputer is moved out of wait mode by a hardware reset, NMI interrupt or peripheral function interrupt. If the microcomputer is to be moved out of exit wait mode by a hardware reset or NMI interrupt, set the peripheral function interrupt priority ILVL2 to ILVL0 bits to "000b" (interrupts disabled) before executing the WAIT instruction. The peripheral function interrupts are affected by the CM02 bit. If CM02 bit is "0" (peripheral function clocks not turned off during wait mode), peripheral function interrupts can be used to exit wait mode. If CM02 bit is "1" (peripheral function clocks turned off during wait mode), the peripheral functions using the peripheral function clocks stop operating, so that only the peripheral functions clocked by external signals can be used to exit wait mode. Table 9.4 Interrupts to Exit Wait Mode and Use Conditions
Interrupt NMI Interrupt Serial Interface Interrupt Key Input Interrupt A/D Conversion Interrupt Timer A Interrupt Timer B Interrupt INT Interrupt Can be used
CM02=0 Can be used Can be used when operating with internal or external clock Can be used Can be used in one-shot mode Can be used in all modes Can be used
CM02=1 Can be used when operating with external clock Can be used -(Do not use) Can be used in event counter mode or when the count source is fC32 Can be used
Table 9.4 lists the Interrupts to Exit Wait Mode and Use Conditions. If the microcomputer is to be moved out of wait mode by a peripheral function interrupt, set up the following before executing the WAIT instruction. (1) Set the ILVL2 to ILVL0 bits in the interrupt control register, for peripheral function interrupts used to exit wait mode. The ILVL2 to ILVL0 bits in all other interrupt control registers, for peripheral function interrupts not used to exit wait mode, are set to "000b" (interrupt disable). (2) Set the I flag to "1". (3) Start operating the peripheral functions used to exit wait mode. When the peripheral function interrupt is used, an interrupt routine is performed as soon as an interrupt request is acknowledged and the CPU clock is supplied again. When the microcomputer exits wait mode by the peripheral function interrupt, the CPU clock is the same clock as the CPU clock executing the WAIT instruction.
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9.4.3
Stop Mode
In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks. Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The least amount of power is consumed in this mode. If the voltage applied to VCC1 and VCC2 pins is VRAM or more, the internal RAM is retained. When applying 2.7 or less voltage to VCC1 and VCC2 pins, make sure VCC1 = VCC2 VRAM. However, the peripheral functions clocked by external signals keep operating. The following interrupts can be used to exit stop mode. Table 9.5 Interrupts to Exit Stop Mode and Use Conditions
Interrupt NMI Interrupt Key Input Interrupt INT Interrupt Timer A Interrupt Timer B Interrupt Serial Interface Interrupt Can be used Can be used Can be used
CM02=1
Can be used when counting external pulses in event counter mode Can be used when operating with external clock
9.4.3.1
Entering Stop Mode
The microcomputer is placed into stop mode by setting the CM10 bit in the CM1 register to "1" (all clocks turned off). At the same time, the CM06 bit in the CM0 register is set to "1" (divide-by-8 mode) and the CM15 bit in the CM1 register is set to "1" (main clock oscillator circuit drive capability high).
9.4.3.2
Pin Status in Stop Mode
Table 9.6 lists Pin Status in Stop Mode. Table 9.6 Pin Status in Stop Mode
Pin A0 to A19, D0 to D15, CS0 to CS3, BHE RD, WR, WRL, WRH HLDA, BCLK ALE I/O ports CLKOUT When fC selected When f8, f32 selected
Memory Expansion Mode Single-Chip Mode Microprocessor Mode Retains status before stop mode Does not become a bus control pin "H" "H" Indeterminate Retains status before stop mode Retains status before stop mode Does not become a CLKOUT pin "H" Retains status before stop mode
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9.4.3.3
Exiting Stop Mode
Stop mode is exited by a hardware reset, NMI interrupt or peripheral function interrupt. When the hardware reset or NMI interrupt is used to exit wait mode, set all ILVL2 to ILVL0 bits in the interrupt control registers for the peripheral function interrupt to "000b" (interrupt disabled) before setting the CM10 bit to "1". When the peripheral function interrupt is used to exit stop mode, set the CM10 bit to "1" after the following settings are completed. (1) Set the ILVL2 to ILVL0 bits in the interrupt control registers to decide the peripheral priority level of the peripheral function interrupt. Set the interrupt priority levels of the interrupts, not being used to exit stop mode, to "0" by setting the all ILVL2 to ILVL0 bits to "000b" (2) Set the I flag to "1". (3) Start operation of peripheral function being used to exit wait mode. When exiting stop mode by the peripheral function interrupt, the interrupt routine is performed when an interrupt request is generated and the CPU clock is supplied again. When stop mode is exited by the peripheral function interrupt or NMI interrupt, the CPU clock source is as follows, in accordance with the CPU clock source setting before the microcomputer had entered stop mode. * When the sub clock is the CPU clock before entering stop mode : Sub clock * When the main clock is the CPU clock source before entering stop mode : Main clock divided by 8
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Figure 9.7 shows the state transition from normal operation mode to stop mode and wait mode. Figure 9.8 shows the State Transition in Normal Operation Mode. Table 9.7 shows a state transition matrix describing Allowed Transition and Setting. The vertical line shows current state and horizontal line shows state after transition.
Reset
CPU operation stopped
All oscillators stopped
CM10=1
Stop mode
Interrupt Interrupt CM07=0 CM06=1 CM05=0 CM10=1(1)
Medium-speed mode (divided-by-8 mode)
WAIT instruction Interrupt WAIT instruction Interrupt
Wait mode
Stop mode
CM10=1
When low power dissipation mode
High-speed, mediumspeed mode
Wait mode
When low-speed mode
CM10=1
Stop mode
Interrupt
Low-speed, low power dissipation mode
WAIT instruction Interrupt
Wait mode
Normal mode
CM05, CM06, CM07 : Bits in CM0 register CM10 : Bit in CM1 register
NOTES : 1. Write to the CM0 and CM1 registers simultaneously per 16 bit. Since the operation starts from the main clock after exiting stop mode, the time until the CPU operates can be reduced.
Figure 9.7
State Transition to Stop Mode and Wait Mode
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Main clock oscillation
High-speed mode CPU clock: f(XIN) CM07=0 CM06=0 CM17=0 CM16=0
Middle-speed mode (divide by 2) CPU clock: f(XIN)/2 CM07=0 CM06=0 CM17=0 CM16=1
Middle-speed mode (divide by 4) CPU clock: f(XIN)/4 CM07=0 CM06=0 CM17=1 CM16=0
Middle-speed mode (divide by 8) CPU clock: f(XIN)/8 CM07=0 CM06=1
Middle-speed mode (divide by 16) CPU clock: f(XIN)/16 CM07=0 CM06=0 CM17=1 CM16=1
CM04=1
CM04=0
High-speed mode CPU clock: f(XIN) CM07=0 CM06=0 CM17=0 CM16=0
Middle-speed mode (divide by 2) CPU clock: f(XIN)/2 CM07=0 CM06=0 CM17=0 CM16=1
Middle-speed mode (divide by 4) CPU clock: f(XIN)/4 CM07=0 CM06=0 CM17=1 CM16=0
Middle-speed mode (divide by 8) CPU clock: f(XIN)/8 CM07=0 CM06=1
Middle-speed mode (divide by 16) CPU clock: f(XIN)/16 CM07=0 CM06=0 CM17=1 CM16=1
CM07=1(2)
CM07=0(1, 3)
Low-speed mode CPU clock: f(XCIN) CM07=1
CM05=1 Low power dissipation mode CPU clock: (XCIN) CM07=1 CM06=1 CM15=1
CM05=0
Sub clock oscillation
NOTES: 1. Wait the main clock oscillation stabilizes. 2. Switch clock after oscillation of sub-clock is sufficiently stable. 3. Change CM17 and CM16 bits in the CM1 register before changing CM06 bit in the CM0 register. 4. Transit in accordance with arrow.
Figure 9.8
State Transition in Normal Operation Mode
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Table 9.7
Allowed Transition and Setting
High-Speed Mode, Middle-Speed Mode Low-Speed Mode State After Transition Low Power Dissipation Mode Stop Mode Wait Mode
Current State
High-Speed Mode, Middle-Speed Mode Low-Speed Mode Low Power Dissipation Mode Stop Mode Wait Mode
(NOTE 4) (8) - (14)(NOTE 1) (14)
(9)(NOTE 3)
- (11)(NOTE 2)
(12) (12) (12)
(13) (13) (13) -
(10) (14) (14) (14) (14)
-
-: Cannot transit NOTES: 1. When exiting stop mode, the CM06 bit is set to "1" (division by 8 mode). 2. If the CM05 bit set to "1" (main clock stop), then the CM06 bit is set to "1" (division by 8 mode). 3. A transition can be made only when sub clock is oscillating. 4. State transitions within the same mode (divide-by-n values changed or subclock oscillation turned on or off) are shown in the table below.
No Division No Division
Sub clock Oscillating
Sub Clock Oscillating Divided Divided Divided by 2 by 4 by 8 (4) (5) (7) (5) (4) (4) (4)
-
Divided by 16 (6) (6) (6) (6)
No Division (1)
- - - -
Sub Clock Turned Off Divided Divided Divided by 2 by 4 by 8 - - - (1)
- - - - - -
Divided by 16 -
- - -
Divided by 2 Divided by 4 Divided by 8 Divided by 16 No Division
(3) (3) (3) (3) (2)
- - - -
(7) (7)
(1)
- -
(5) (5)
- -
(1)
-
(7)
- - - - - - -
(1) (6) (6) (6) (6)
(4) (3) (3) (3) (3) (4) (4) (4)
(5) (5)
(7) (7) (7)
Sub clock Turned Off
Divided by 2 Divided by 4 Divided by 8 Divided by 16
(2)
- - -
(2)
- -
(2)
-
(5) (5) (7)
(2)
-: Cannot transit
5. ( ) : setting method. See the following table. (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) Setting CM04 = 0 CM04 = 1 CM06 = 0, CM17 = 0, CM16 = 0 CM06 = 0, CM17 = 0, CM16 = 1 CM06 = 0, CM17 = 1, CM16 = 0 CM06 = 0, CM17 = 1, CM16 = 1 CM06 = 1 CM07 = 0 CM07 = 1 CM05 = 0 CM05 = 1 CM10 = 1 Wait Instruction Hardware Interrupt Operation Sub clock turned off Sub clock oscillating CPU clock no division mode CPU clock division by 2 mode CPU clock division by 4 mode CPU clock division by 16 mode CPU clock division by 8 mode Main clock selected Sub clock selected Main clock oscillating Main clock turned off Transition to stop mode Transition to wait mode Exit stop mode or wait mode
CM04, CM05, CM06, CM07 : Bits in CM0 register CM10, CM16, CM17 : Bits in CM1 register
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10. Protection
10. Protection
In the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily. Figure 10.1 shows the PRCR Register. The following lists the registers protected by the PRCR register. * The PRC0 bit protects the CM0, CM1 and PCLKR registers; * The PRC1 bit protects the PM0 and PM1 registers; * The PRC2 bit protects the PD9 register; Set the PRC2 bit to "1" (write enabled) and then write to any address, and the PRC2 bit will be cleared to "0" (write protected). The registers protected by the PRC2 bit should be changed in the next instruction after setting the PRC2 bit to "1". Make sure no interrupts or DMA transfers will occur between the instruction in which the PRC2 bit is set to "1" and the next instruction. The PRC0 and PRC1 bits are not automatically cleared to "0" by writing to any address. They can only be cleared in a program.
Protect Register
b7 b6 b5 b4 b3 b2 b1 b0
000
Symbol PRCR Bit Symbol PRC0
Address 000Ah Bit Name Protect Bit 0
After Reset XX000000b Function Enable w rite to CM0, CM1 and PCLKR registers 0 : Write protected 1 : Write enabled Enable w rite to PM0 and PM1 registers 0 : Write protected 1 : Write enabled (1) Enable w rite to PD9 register 0 : Write protected 1 : Write enabled (1) Set to "0". RW RW
Protect Bit 1 PRC1 Protect Bit 2 PRC2 -- (b5-b3) -- (b7-b6) Reserved Bit
RW
RW
RW --
Nothing is assigned. When w rite, set to "0". When read, its content is indeterminate.
NOTES : 1. The PRC2 bit is set to "0" by w riting to any address after setting it to "1". Other bits are not set to "0" by w riting to any address, and must therefore be set in a program.
Figure 10.1
PRCR Register
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11. Interrupt
11. Interrupt
11.1 Type of Interrupts
Figure 11.1 shows Type of Interrupts.
Software (Non-maskable interrupt)
Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction INT instruction
Interrupt Special (Non-maskable interrupt) Hardware Peripheral function (1) (Maskable interrupt)
NMI DBC (2) Watchdog timer Single step (2) Address match
NOTES: 1. The peripheral functions in the microcomputer are used to generate the peripheral interrupt. 2. Do not normally use this interrupt because it is provided exclusively for use by development tools.
Figure 11.1
Type of Interrupts
* Maskable Interrupt
: An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority can be changed by priority level. * Non-Maskable Interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority cannot be changed by priority level.
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11. Interrupt
11.2
Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts.
11.2.1
Undefined Instruction Interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
11.2.2
Overflow Interrupt
An overflow interrupt occurs when executing the INTO instruction with the O flag set to "1" (the operation resulted in an overflow). The following are instructions whose O flag changes by arithmetic: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
11.2.3
BRK Interrupt
A BRK interrupt occurs when executing the BRK instruction.
11.2.4
INT Instruction Interrupt
An INT instruction interrupt occurs when executing the INT instruction. Software interrupt Nos. 0 to 63 can be specified for the INT instruction. Because software interrupt Nos. 4 to 31 are assigned to peripheral function interrupts, the same interrupt routine as for peripheral function interrupts can be executed by executing the INT instruction. In software interrupt Nos. 0 to 31, the U flag is saved to the stack during instruction execution and is cleared to "0" (ISP selected) before executing an interrupt sequence. The U flag is restored from the stack when returning from the interrupt routine. In software interrupt Nos. 32 to 63, the U flag does not change state during instruction execution, and the SP then selected is used.
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11. Interrupt
11.3
Hardware Interrupts
Hardware interrupts are classified into two types - special interrupts and peripheral function interrupts.
11.3.1
Special Interrupts
Special interrupts are non-maskable interrupts.
11.3.1.1
NMI Interrupt
An NMI interrupt is generated when input on the NMI pin changes state from high to low. For details about the NMI interrupt, refer to the 11.7 NMI Interrupt.
11.3.1.2
DBC Interrupt
Do not normally use this interrupt because it is provided exclusively for use by development tools.
11.3.1.3
Watchdog Timer Interrupt
Generated by the watchdog timer. Once a watchdog timer interrupt is generated, be sure to initialize the watchdog timer. For details about the watchdog timer, refer to the 12. Watchdog Timer.
11.3.1.4
Single-Step Interrupt
Do not normally use this interrupt because it is provided exclusively for use by development tools.
11.3.1.5
Address Match Interrupt
An address match interrupt is generated immediately before executing the instruction at the address indicated by the RMAD0 to RMAD1 register that corresponds to one of the AIER0 or AIER1 bit in the AIER register which is "1" (address match interrupt enabled). For details about the address match interrupt, refer to the 11.9 Address Match Interrupt.
11.3.2
Peripheral Function Interrupts
The peripheral function interrupt occurs when a request from the peripheral functions in the microcomputer is acknowledged. The peripheral function interrupt is a maskable interrupt. See Table 11.2 Relocatable Vector Tables about how the peripheral function interrupt occurs. Refer to the descriptions of each function for details.
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11. Interrupt
11.4
Interrupts and Interrupt Vector
One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the corresponding interrupt vector. Figure 11.2 shows the Interrupt Vector.
MSB
LSB Low-order address Middle-order address 0000 High-order address 0000
Vector address (L)
Vector address (H)
Figure 11.2 Interrupt Vector
0000
11.4.1
Fixed Vector Tables
The fixed vector tables are allocated to the addresses from FFFDCh to FFFFFh. Table 11.1 lists the Fixed Vector Tables. In the one time flash memory and the flash memory version of microcomputer, the vector addresses (H) of fixed vectors are used by the ID code check function. For details, refer to the 19.2 Functions To Prevent Flash Memory from Rewriting . Table 11.1 Fixed Vector Tables
Interrupt Source Undefined Instruction (UND instruction) Overflow (INTO instruction) BRK Instruction (2) Address Match Single Step (1) Watchdog Timer DBC
(1)
Vector Table Addresses Address (L) to Address (H) FFFDCh to FFFDFh FFFE0h to FFFE3h FFFE4h to FFFE7h FFFE8h to FFFEBh FFFECh to FFFEFh FFFF0h to FFFF3h FFFF4h to FFFF7h FFFF8h to FFFFBh FFFFCh to FFFFFh
Reference M16C/60, M16C/20 Series software manual 11.9 Address Match Interrupt 12. Watchdog Timer 11.7 NMI interrupt 5. Reset
NMI Reset
NOTES: 1. Do not normally use this interrupt because it is provided exclusively for use by development tools. 2. If the contents of address FFFE7h is FFh, program execution starts from the address shown by the vector in the relocatable vector table.
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11. Interrupt
11.4.2
Relocatable Vector Tables
The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable vector table area. Table 11.2 lists the Relocatable Vector Tables. Setting an even address in the INTB register results in the interrupt sequence being executed faster than in the case of odd addresses. Table 11.2 Relocatable Vector Tables
Vector Address (1) Address (L) to Address (H) +0 to +3 (0000h to 0003h) - +16 to +19 (0010h to 0013h)
- +24 to +27 (0018h to 001Bh) +28 to +31 (001Ch to 001Fh) - +36 to +39 (0024h to 0027h)
Interrupt Source BRK Instruction (5) -(Reserved) INT3 - UART1 Bus Collision Detect (4, 6) UART0 Bus Collision Detect (4, 6) - INT4 (2) UART 2 Bus Collision Detection (6) DMA0 DMA1 Key Input Interrupt A/D UART2 Transmit, NACK2 (3) UART2 Receive, ACK2 (3) UART0 Transmit, NACK0 (3) UART0 Receive, ACK0 (3) UART1 Transmit, NACK1 (3) UART1 Receive, ACK1 (3) Timer A0 Timer A1 Timer A2 - - Timer B0 Timer B1 Timer B2 INT0 INT1 INT2 Software Interrupt (5)
Software Interrupt Reference Number 0 M16C/60, M16C/20 Series software manual 1 to 3 4 11.6 INT interrupt 5 - 6 15. Serial Interface 7 8 - 9 11.6 INT interrupt 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 to 63 M16C/60, M16C/20 Series software manual 15. Serial Interface 13. DMAC 11.8 Key Input Interrupt 16. A/D Converter 15. Serial Interface
+40 to +43 (0028h to 002Bh) +44 to +47 (002Ch to 002Fh) +48 to +51 (0030h to 0033h) +52 to +55 (0034h to 0037h) +56 to +59 (0038h to 003Bh) +60 to +63 (003Ch to 003Fh) +64 to +67 (0040h to 0043h) +68 to +71 (0044h to 0047h) +72 to +75 (0048h to 004Bh) +76 to +79 (004Ch to 004Fh) +80 to +83 (0050h to 0053h) +84 to +87 (0054h to 0057h) +88 to +91 (0058h to 005Bh) +92 to +95 (005Ch to 005Fh) - - +104 to +107 (0068h to 006Bh) +108 to +111 (006Ch to 006Fh) +112 to +115 (0070h to 0073h) +116 to +119 (0074h to 0077h) +120 to +123 (0078h to 007Bh) +124 to +127 (007Ch to 007Fh) +128 to +131 (0080h to 0083h) to +252 to +255 (00FCh to 00FFh)
14. Timers
- - 14. Timers
11.6 INT interrupt
NOTES: 1. Address relative to address in INTB. 2. Use the IFSR6 bit in the IFSR register to select. 3. During I2C mode, NACK and ACK interrupts comprise the interrupt source. 4. Use the IFSR26 and IFSR27 bits in the IFSR2A register to select. 5. These interrupts cannot be disabled using the I flag. 6. Bus collision detection : During IE mode, this bus collision detection constitutes the factor of an interrupt. During I2C mode, however, a start condition or a stop condition detection constitutes the factor of an interrupt.
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11. Interrupt
11.5
Interrupt Control
The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted. What is explained here does not apply to nonmaskable interrupts. Use the I flag in the FLG register, IPL, and ILVL2 to ILVL0 bits in the each interrupt control register to enable/ disable the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in the each interrupt control register. Figure 11.3 and 11.4 shows the Interrupt Control Registers.
Interrupt Control Register (2)
Symbol U1BCNIC(3) U0BCNIC(3) BCNIC DM0IC, DM1IC KUPIC ADIC S0TIC to S2TIC S0RIC to S2RIC TA0IC to TA2IC TB0IC to TB2IC Address 0046h 0047h 004Ah 004Bh, 004Ch 004Dh 004Eh 0051h, 0053h, 004Fh 0052h, 0054h, 0050h 0055h to 0057h 005Ah to 005Ch After Reset XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b
b7 b6 b5 b4 b3 b2 b1 b0
Bit Symbol ILVL0
Bit Name Interrupt Priority Level Select Bit
b2 b1 b0
Function 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7
RW RW
ILVL1
RW
ILVL2 Interrupt Request Bit
RW
IR -- (b7-b4)
0 : Interrupt not requested 1 : Interrupt requested
RW(1) --
Nothing is assigned.When w rite, set to "0". When read, their contents are indeterminate.
NOTES : 1. This bit can only be reset by w riting "0" (Do not w rite "1"). 2. To rew rite the interrupt control registers, do so at a point that does not generate the interrupt request for that register. For details, refer to 21.5 Precautions for Interrupt. 3. Use the IFSR2A register to select.
Figure 11.3
Interrupt Control Registers (1)
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11. Interrupt
INTi (0 to 4) Interrupt Control Register (2)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol INT3IC (4) INT4IC (4) INT0IC to INT2IC Bit Symbol ILVL0
Address 0044h 0049h 005Dh to 005Fh Bit Name
b2 b1 b0
After Reset XX00X000b XX00X000b XX00X000b Function 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 RW RW
Interrupt Priority Level Select Bit
ILVL1
RW
ILVL2 Interrupt Request Bit Polarity Select Bit Reserved Bit
RW
IR POL -- (b5) -- (b7-b6)
0: Interrupt not requested 1: Interrupt requested 0 : Selects falling edge (3) 1 : Selects rising edge Set to "0".
RW(1) RW RW --
Nothing is assigned. When w rite, set to "0". When read, their contents are indeterminate.
NOTES : 1. This bit can only be reset by w riting "0" (Do not w rite "1"). 2. To rew rite the interrupt control register, do so at a point that does not generate the interrupt request for that register. For details, refer to 21.5 Precautions for Interrupt. 3. If the IFSRi bit (i = 0 to 4) in the IFSR register are "1" (both edges), set the POL bit in the INTiIC register to "0" (falling edge). 4. When the BYTE pin is low and the processor mode is memory expansion or microprocessor mode, set the ILVL2 to ILVL0 bits in the INT4IC to INT3IC registers to "000b" (interrupts disabled).
Figure 11.4
Interrupt Control Registers (2)
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11. Interrupt
11.5.1
I Flag
The I flag enables or disables the maskable interrupt. Setting the I flag to "1" (= enabled) enables the maskable interrupt. Setting the I flag to "0" (= disabled) disables all maskable interrupts.
11.5.2
IR Bit
The IR bit is set to "1" (= interrupt requested) when an interrupt request is generated. Then, when the interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is cleared to "0" (= interrupt not requested). The IR bit can be cleared to "0" in a program. Note that do not write "1" to this bit.
11.5.3
ILVL2 to ILVL0 Bits and IPL
Interrupt priority levels can be set using the ILVL2 to ILVL0 bits. Table 11.3 shows the Settings of Interrupt Priority Levels and Table 11.4 shows the Interrupt Priority Levels Enabled by IPL. The following are conditions under which an interrupt is accepted: * I flag = 1 * IR bit = 1 * interrupt priority level > IPL The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. In no case do they affect one another.
Table 11.3 Settings of Interrupt Priority Levels
ILVL2 to ILVL0 Bits 000b 001b 010b 011b 100b 101b 110b 111b Interrupt Priority Level Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 High Priority Order - Low
Table 11.4Interrupt Priority Levels Enabled by IPL
IPL 000b 001b 010b 011b 100b 101b 110b 111b Enabled Interrupt Priority Levels Interrupt levels 1 and above are enabled Interrupt levels 2 and above are enabled Interrupt levels 3 and above are enabled Interrupt levels 4 and above are enabled Interrupt levels 5 and above are enabled Interrupt levels 6 and above are enabled Interrupt levels 7 and above are enabled All maskable interrupts are disabled
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11. Interrupt
11.5.4
Interrupt Sequence
An interrupt sequence - what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed - is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. The CPU behavior during the interrupt sequence is described below. Figure 11.5 shows Time Required for Executing Interrupt Sequence. (1) The CPU obtains interrupt information (interrupt number and interrupt request level) by reading address 000000h. Then, the IR bit applicable to the interrupt information is set to "0" (interrupt requested). (2) The FLG register, prior to an interrupt sequence, is saved to a temporary register (1) within the CPU. (3) The I, D and U flags in the FLG register become as follows: * The I flag is set to "0" (interrupt disabled) * The D flag is set to "0" (single-step interrupt disabled) * The U flag is set to "0" (ISP selected) However, the U flag does not change state if an INT instruction for software interrupt Nos. 32 to 63 is executed. (4) The temporary register (1) within the CPU is saved to the stack. (5) The PC is saved to the stack. (6) The interrupt priority level of the acknowledged interrupt in IPL is set. (7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC. After the interrupt sequence is completed, an instruction is executed from the starting address of the interrupt routine. NOTES: 1.Temporary register cannot be modified by users.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
CPU clock Address bus Data bus Address 00000h
Interrupt information
Indeterminate(1) Indeterminate(1)
SP-2 SP-2 contents
SP-4 SP-4 contents
vec vec contents
vec+2 vec+2 contents
PC
NOTES : 1. The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the instruction queue buffer is ready to accept instructions.
Figure 11.5
Time Required for Executing Interrupt Sequence
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11. Interrupt
11.5.5
Interrupt Response Time
Figure 11.6 shows the Interrupt Response Time. The interrupt response or interrupt acknowledge time denotes a time from when an interrupt request is generated till when the first instruction in the interrupt routine is executed. Specifically, it consists of a time from when an interrupt request is generated till when the instruction then executing is completed ((a) on Figure 11.6) and a time during which the interrupt sequence is executed ((b) on Figure 11.6).
Interrupt request generated
Interrupt request acknowledged Time
Instruction (a)
Interrupt sequence (b)
Instruction in interrupt routine
Interrupt response time
(a) A time from when an interrupt request is generated till when the instruction then executing is completed. The length of this time varies with the instruction being executed. The DIVX instruction requires the longest time, which is equal to 30 cycles (without wait state, the divisor being a register). (b) A time during which the interrupt sequence is executed. For details, see the table below. Note, however, that the values in this table must be increased 2 cycles for the DBC interrupt and 1 cycle for the address match and single-step interrupts.
Interrupt Vector Address SP Value 16-Bit Bus, Without Wait 8-Bit Bus, Without Wait Even Even Odd Odd Even Odd Even Odd 18 cycles 19 cycles 19 cycles 20 cycles 20 cycles 20 cycles 20 cycles 20 cycles
Figure 11.6
Interrupt Response Time
11.5.6
Variation of IPL when Interrupt Request is Accepted
When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL. When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed in Table 11.5 is set in the IPL. Table 11.5 lists the IPL Level That is Set to IPL When a Software or Special Interrupt is Accepted. Table 11.5 IPL Level That is Set to IPL When a Software or Special Interrupt is Accepted
Interrupt Sources Watchdog Timer, NMI Software, Address Match, DBC, Single-Step 7
Level that is Set to IPL Not changed
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11. Interrupt
11.5.7
Saving Registers
In the interrupt sequence, the FLG register and PC are saved to the stack. At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits in the FLG register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved. Figure 11.7 shows the Stack Status Before and After Acceptance of Interrupt Request. The other necessary registers must be saved in a program at the beginning of the interrupt routine. Use the PUSHM instruction, and all registers except SP can be saved with a single instruction.
Address MSB
Stack LSB
Address MSB
Stack LSB [SP] New SP value
m-4 m-3 m-2 m-1 m m+1 Content of previous stack Content of previous stack [SP] SP value before interrupt request is accepted.
m-4 m-3 m-2 m-1 m m+1 FLGH
PCL PCM FLGL PCH
Content of previous stack Content of previous stack
Stack status before interrupt request is acknowledged
PCH : 4 high-order bits of PC PCM : 8 middle-order bits of PC PCL : 8 low-order bits of PC
Stack status after interrupt request is acknowledged
FLGH : 4 high-order bits of FLG FLGL : 8 low-order bits of FLG
Figure 11.7
Stack Status Before and After Acceptance of Interrupt Request
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11. Interrupt
The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP (1), at the time of acceptance of an interrupt request, is even or odd. If the stack pointer (1) is even, the FLG register and the PC are saved,16 bits at a time. If odd, they are saved in two steps, 8 bits at a time. Figure 11.8 shows the Operation of Saving Register. NOTES: 1.When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated by the U flag. Otherwise, it is the ISP.
(1) SP contains even number
Address Stack Sequence in which order registers are saved
[SP] - 5 (Odd) [SP] - 4 (Even) [SP] - 3(Odd) [SP] - 2 (Even) [SP] - 1(Odd) [SP] (Even) Finished saving registers in two operations. FLGH PCL PCM FLGL PCH (1) Saved simultaneously, all 16 bits (2) Saved simultaneously, all 16 bits
(2) SP contains odd number
Address Stack Sequence in which order registers are saved
[SP] - 5 (Even) [SP] - 4(Odd) [SP] - 3 (Even) [SP] - 2(Odd) [SP] - 1 (Even) [SP] (Odd) Finished saving registers in four operations. PCH : 4 high-order bits of PC PCM : 8 middle-order bits of PC PCL : 8 low-order bits of PC FLGH : 4 high-order bits of FLG FLGL : 8 low-order bits of FLG FLGH PCL PCM FLGL PCH (3) (4) Saved, 8 bits at a time (1) (2)
NOTES : 1. [SP] denotes the initial value of the SP when interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4.
Figure 11.8
Operation of Saving Register
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11. Interrupt
11.5.8
Returning from an Interrupt Routine
The FLG register and PC in the state in which they were immediately before entering the interrupt sequence are restored from the stack by executing the REIT instruction at the end of the interrupt routine. Thereafter the CPU returns to the program which was being executed before accepting the interrupt request. Return the other registers saved by a program within the interrupt routine using the POPM or similar instruction before executing the REIT instruction.
11.5.9
Interrupt Priority
If two or more interrupt requests are generated while executing one instruction, the interrupt request that has the highest priority is accepted. For maskable interrupts (peripheral functions), any desired priority level can be selected using the ILVL2 to ILVL0 bits. However, if two or more maskable interrupts have the same priority level, their interrupt priority is resolved by hardware, with the highest priority interrupt accepted. The watchdog timer and other special interrupts have their priority levels set in hardware. Figure 11.9 shows the Hardware Interrupt Priority. Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches invariably to the interrupt routine.
Reset NMI DBC Watchdog Timer Peripheral function Single step Address match
Figure 11.9 Hardware Interrupt Priority
High
Low
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11. Interrupt
11.5.10 Interrupt Priority Resolution Circuit
The interrupt priority resolution circuit is used to select the interrupt with the highest priority among those requested. Figure 11.10 shows the Interrupts Priority Select Circuit.
Priority level of each interrupt INT1 Timer B2 Timer B0 Timer A1 UART1 bus collision INT3 INT2 INT0 Timer B1 Timer A2 UART0 bus collision UART1 reception, ACK1 UART0 reception, ACK0 UART2 reception, ACK2 A/D conversion DMA1 UART 2 bus collision Timer A0 UART1 transmission, NACK1 UART0 transmission, NACK0 UART2 transmission, NACK2 Key input interrupt DMA0 INT4 IPL
Level 0 (initial value)
Highest
Priority of peripheral function interrupts (if priority levels are same)
Lowest
Interrupt request level resolution output to clock generating circuit (Figure 9.1 Clock Generation Circuit)
I flag Address match Watchdog timer DBC NMI
Interrupt request accepted
Figure 11.10
Interrupts Priority Select Circuit
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11. Interrupt
11.6
INT Interrupt
INTi interrupt (i=0 to 4) is triggered by the edges of external inputs. The edge polarity is selected using the IFSRi bit in the IFSR register. To use the INT4 interrupt, set the IFSR6 bit in the IFSR register to "1" (= INT4). After modifying the IFSR6 bit, clear the corresponding IR bit to "0" (= interrupt not requested) before enabling the interrupt. Figure 11.11 shows the IFSR and IFSR2A Registers.
Interrupt Factor Select Register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol IFSR Bit Symbol IFSR0 IFSR1 IFSR2 IFSR3 IFSR4 -- (b5) IFSR6 -- (b7)
Address 035Fh Bit Name INT0 Interrupt Polarity Sw itching Bit INT1 Interrupt Polarity Sw itching Bit INT2 Interrupt Polarity Sw itching Bit INT3 Interrupt Polarity Sw itching Bit INT4 Interrupt Polarity Sw itching Bit Reserved Bit Interrupt Request Factor Select Bit Reserved Bit
After Reset 00h Function 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges Set to "0". 0 : Do not set
_____
(1)
RW RW RW RW RW RW RW RW RW
(1)
(1)
(1)
(1)
1 : INT4 Set to "0".
NOTES : 1. When setting this bit to "1" (= both edges), make sure the POL bit in the INT0IC to INT4IC register are set to "0" (= falling edge).
Interrupt Factor Select Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol IFSR2A Bit Symbol -- (b5-b0) IFSR26 IFSR27
Address 035Eh Bit Name Nothing is assigned. When w rite, set to "0". When read, their contents are indeterminate. Interrupt Request Factor Select Bit (1) Interrupt Request Factor Select Bit (2)
After Reset 00XXXXXXb Function RW -- RW RW
0 : Do not set 1 : UART0 bus collision detection 0 : Do not set 1 : UART1 bus collision detection
NOTES : 1. When using UART0 bus collision detection, set the IFSR26 bit to "1". 2. When using UART1 bus collision detection, set the IFSR27 bit to "1".
Figure 11.11
IFSR and IFSR2A Registers
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11. Interrupt
11.7
NMI Interrupt
An NMI interrupt request is generated when input on the NMI pin changes state from high to low. The NMI interrupt is a non-maskable interrupt. The input level of this NMI interrupt input pin can be read by accessing the P8_5 bit in the P8 register. This pin cannot be used as an input port.
11.8
Key Input Interrupt
Of P10_4 to P10_7, a key input interrupt is generated when input on any of the P10_4 to P10_7 pins which has had the PD10_4 to PD10_7 bits in the PD10 register set to "0" (= input) goes low. Key input interrupts can be used as a key-on wake up function, the function which gets the microcomputer out of wait or stop mode. However, if you intend to use the key input interrupt, do not use P10_4 to P10_7 as analog input ports. Figure 11.12 shows the block diagram of the Key Input Interrupt. Note, however, that while input on any pin which has had the PD10_4 to PD10_7 bits set to "0" (= input mode) is pulled low, inputs on all other pins of the port are not detected as interrupts.
PU25 bit in the PUR2 register Pull-up transistor PD10_7 bit in the PD10 register PD10_7 bit in the PD10 register KI3 Pull-up transistor KI2 Pull-up transistor KI1 PD10_4 bit in the PD10 register PD10_5 bit in the PD10 register PD10_6 bit in the PD10 register
Interrupt control circuit
KUPIC register
Key input interrupt request
Pull-up transistor KI0
Figure 11.12
Key Input Interrupt
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11. Interrupt
11.9
Address Match Interrupt
An address match interrupt request is generated immediately before executing the instruction at the address indicated by the RMADi register (i=0 to 1). Set the start address of any instruction in the RMADi register. Use the AIER0 and AIER1 bits in the AIER register to enable or disable the interrupt. Note that the address match interrupt is unaffected by the I flag and IPL. For address match interrupts, the value of the PC that is saved to the stack area varies depending on the instruction being executed (refer to 11.5.7 Saving Registers). (The value of the PC that is saved to the stack area is not the correct return address.) Therefore, follow one of the methods described below to return from the address match interrupt. * Rewrite the content of the stack and then use the REIT instruction to return. * Restore the stack to its previous state before the interrupt request was accepted by using the POP or similar other instruction and then use a jump instruction to return. Table 11.6 shows the Value of the PC that is Saved to the Stack Area when an Address Match Interrupt Request is Accepted The address match interrupt is not available for an external space when an 8-bit wide external data bus is used. Figure 11.13 shows the AIER and RMAD0 to RMAD1 Registers. Table 11.6 Value of the PC that is Saved to the Stack Area when an Address Match Interrupt Request is Accepted
Instruction at the Address Indicated by the RMADi Register * 16-bit op-code instruction * Instruction shown below among 8-bit operation code instructions ADD.B:S #IMM8,dest SUB.B:S #IMM8,dest AND.B:S OR.B:S #IMM8,dest MOV.B:S #IMM8,dest STZ.B:S STNZ.B:S #IMM8,dest STZX.B:S #IMM81,#IMM82,dest CMP.B:S #IMM8,dest PUSHM src POPM dest JMPS #IMM8 JSRS #IMM8 MOV.B:S #IMM,dest (However, dest=A0 or A1) Instructions other than the above
Value of the PC that is saved to the stack area
#IMM8,dest #IMM8,dest
The address indicated by the RMADi register +2
The address indicated by the RMADi register +1
Value of the PC that is saved to the stack area : Refer to 11.5.7 Saving Registers.
Table 11.7
Relationship Between Address Match Interrupt Sources and Associated Registers
Address Match Interrupt Enable Bit AIER0 AIER1 Address Match Interrupt Register RMAD0 RMAD1
Address Match Interrupt sources Address Match Interrupt 0 Address Match Interrupt 1
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11. Interrupt
Address Match Interrupt Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol AIER Bit Symbol AIER0 AIER1 -- (b7-b2)
Address 0009h Bit Name Address Match Interrupt 0 Enable Bit Address Match Interrupt 1 Enable Bit
After Reset XXXXXX00b Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled RW RW RW --
Nothing is assigned. When w rite, set to "0". When read, their contents are indeterminate.
Address Match Interrupt Register i (i = 0 to 1)
(b23) b7 (b19) b3 (b16) (b15) b0 b7 (b8) b0 b7 b0
Symbol RMAD0 RMAD1 Function Address setting register for address match interrupt Nothing is assigned. When w rite, set to "0". When read, their contents are indeterminate.
Address 0012h to 0010h 0016h to 0014h
After Reset X00000h X00000h Setting Range 00000h to FFFFFh RW RW --
Figure 11.13
AIER and RMAD0 to RMAD1 Registers
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12. Watchdog Timer
12. Watchdog Timer
The watchdog timer is the function of detecting when the program is out of control. Therefore, we recommend using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit counter which counts down the clock derived by dividing the CPU clock using the prescaler. A watchdog timer interrupt is generated when an underflow occurs in the watchdog timer. When the main clock source is selected for CPU clock, the divide-by-N value for the prescaler can be chosen to be 16 or 128. If a sub-clock is selected for CPU clock, the divide-by-N value for the prescaler is always 2 no matter how the WDC7 bit is set. The period of watchdog timer can be calculated as given below. The period of watchdog timer is, however, subject to an error due to the prescaler. With main clock chosen for CPU clock Watchdog timer period = Prescaler dividing (16 or 128) x Watchdog timer count (32768) CPU clock
With sub-clock chosen for CPU clock Watchdog timer period = Prescaler dividing (2) x Watchdog timer count (32768) CPU clock
For example, when CPU clock = 16 MHz and the divide-by-N value for the prescaler= 16, the watchdog timer period is approx. 32.8 ms. The watchdog timer is initialized by writing to the WDTS register. The prescaler is initialized after reset. Note that the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is activated to start counting by writing to the WDTS register. In stop mode, wait mode, and hold state, the watchdog timer and prescaler are stopped. Counting is resumed from the held value when the modes or state are released. Figure 12.1 shows the Watchdog Timer Block Diagram. Figure 12.2 shows the WDC and WDTS Register.
Prescaler
CM07 = 0 WDC7 = 0
1/16
CPU clock HOLD
CM07 = 1 CM07 = 0 WDC7 = 1
1/128 1/2
Watchdog timer
Watchdog timer interrupt request
Set to "7FFFh" Write to WDTS register Internal RESET signal ("L" active)
CM07: Bit in CM0 register WDC7: Bit in WDC register
Figure 12.1
Watchdog Timer Block Diagram
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12. Watchdog Timer
Watchdog Timer Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol Address 000Fh WDC Bit Symbol Bit Name High-order Bit of Watchdog Timer -- (b4-b0) WDC5 -- (b6) WDC7 Cold Start / Warm Start Discrimination Flag(1, 2) Reserved Bit Prescaler Select Bit
After Reset 00XXXXXXb Function
RW RO
0 : Cold Start 1 : Warm Start Set to "0" 0 : Divided by 16 1 : Divided by 128
RW RW RW
NOTES : 1. Writing to the WDC register causes the WDC5 bit to be set to "1" (w arm start). If the voltage applied to VCC1 is less than 4.0 V, either w rite to this register w hen the CPU clock frequency is 2 MHz or w rite tw ice. 2. The WDC5 bit is set to "0" (cold start) w hen pow er is turned on and can be set to "1" by program only.
Watchdog Timer Start Register (1)
b7 b0
Symbol WDTS
Address 000Eh
After Reset Indeterminate RW WO
Function The w atchdog timer is initialized and starts counting after a w rite instruction to this register. The w atchdog timer value is alw ays initialized to "7FFFh" regardless of w hatever value is w ritten. NOTES : 1. Write to the WDTS register after the w atchdog timer interrupt occurs.
Figure 12.2
WDC and WDTS Register
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13. DMAC
13. DMAC
The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention. Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8 or 16-bit) data from the source address to the destination address. The DMAC uses the same data bus as used by the CPU. Because the DMAC has higher priority of bus control than the CPU and because it makes use of a cycle steal method, it can transfer one word (16 bits) or one byte (8 bits) of data within a very short time after a DMA request is generated. Figure 13.1 shows the DMAC Block Diagram. Table 13.1 lists the DMAC Specifications. Figures 13.2 to 13.4 shows the DMACrelated registers.
Address bus DMA0 source pointer SAR0(20) (addresses 0022h to 0020h) DMA0 destination pointer DAR0 (20) (addresses 0026h to 0024h) DMA0 forward address pointer (20) (1) DMA0 transfer counter reload register TCR0 (16) (addresses 0029h, 0028h) DMA0 transfer counter TCR0 (16) DMA1 transfer counter reload register TCR1 (16) (addresses 0039h, 0038h) DMA1 transfer counter TCR1 (16) DMA latch high-order bits DMA latch low-order bits DMA1 source pointer SAR1 (20) (addresses 0032h to 0030h) DMA1 destination pointer DAR1 (20) (addresses 0036h to 0034h) DMA1 forward address pointer (20) (1)
Data bus low-order bits
Data bus high-order bits NOTES : 1. Pointer is incremented by a DMA request.
Figure 13.1
DMAC Block Diagram
A DMA request is generated by a write to the DSR bit in the DMiSL register (i = 0 to 1), as well as by an interrupt request which is generated by any function specified by the DMS and DSEL3 to DSEL0 bits in the DMiSL register. However, unlike in the case of interrupt requests, DMA requests are not affected by the I flag and the interrupt control register, so that even when interrupt requests are disabled and no interrupt request can be accepted, DMA requests are always accepted. Furthermore, because the DMAC does not affect interrupts, the IR bit in the interrupt control register does not change state due to a DMA transfer. A data transfer is initiated each time a DMA request is generated when the DMAE bit in the DMiCON register = 1 (DMA enabled). However, if the cycle in which a DMA request is generated is faster than the DMA transfer cycle, the number of transfer requests generated and the number of times data is transferred may not match. Refer to 13.4 DMA Request for details.
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13. DMAC
Table 13.1
DMAC Specifications
Specification 2 (cycle steal method) * From any address in the 1-Mbyte space to a fixed address * From a fixed address to any address in the 1-Mbyte space * From a fixed address to a fixed address 128 Kbytes (with 16-bit transfers) or 64 Kbytes (with 8-bit transfers)
Item No. of Channels Transfer Memory Space
Falling edge of INT0 or INT1 Both edge of INT0 or INT1 Timer A0 to timer A2 interrupt requests Timer B0 to timer B2 interrupt requests UART0 transfer, UART0 reception interrupt requests UART1 transfer, UART1 reception interrupt requests UART2 transfer, UART2 reception interrupt requests A/D conversion interrupt requests Software triggers Channel Priority DMA0 > DMA1 (DMA0 takes precedence) Transfer Unit 8 bits or 16 bits Transfer Address Direction Forward or fixed (The source and destination addresses cannot both be in the forward direction.) Transfer Mode Single Transfer Transfer is completed when the DMAi transfer counter (i = 0 to 1) underflows after reaching the terminal count. Repeat Transfer When the DMAi transfer counter underflows, it is reloaded with the value of the DMAi transfer counter reload register and a DMA transfer is continued with it. DMA Interrupt Request Generation Timing When the DMAi transfer counter underflowed DMA Start up Data transfer is initiated each time a DMA request is generated when the DMAE bit in the DMAiCON register = 1 (enabled). DMA Shutdown Single Transfer * When the DMAE bit is set to "0" (disabled) * After the DMAi transfer counter underflows Repeat Transfer When the DMAE bit is set to "0" (disabled) Reload Timing for Forward Address Pointer When a data transfer is started after setting the DMAE bit to "1" and Transfer Counter (enabled), the forward address pointer is reloaded with the value of the SARi or the DARi pointer whichever is specified to be in the forward direction and the DMAi transfer counter is reloaded with the value of the DMAi transfer counter reload register. DMA Transfer Cycles Minimum 3 cycles between SFR and internal RAM NOTES: 1. DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the I flag nor by the interrupt control register. 2. The selectable factors of DMA requests differ with each channel. 3. Make sure that no DMAC-related registers (addresses 0020h to 003Fh) are accessed by the DMAC.
Maximum No. of Bytes Transferred DMA Request Factors (1, 2)
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13. DMAC
DMA0 Request Factor Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address 03B8h DM0SL Bit Name Bit Symbol DSEL0 DMA Request Factor Select Bit (NOTE 1) DSEL1 DSEL2 DSEL3 -- Nothing is assigned. When w rite, set to "0". (b5-b4) When read, their content are "0". DMS DMA Request Factor Expansion Select Bit Softw are DMA Request Bit DSR
After Reset 00h Function
RW RW RW RW RW -- RW
0: Basic factor of request 1: Extended factor of request A DMA request is generated by setting this bit to "1" w hen the DMS bit is "0" (basic factor) and the DSEL3 to DSEL0 bits are "0001b" (softw are trigger). The value of this bit w hen read is "0".
RW
NOTES : 1. The factors of DMA0 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the manner described below . DMS=1(Extended Factor of Request) DSEL3 to DSEL0 DMS=0(Basic Factor of Request) _____ -- 0000b Falling Edge of INT0 Pin Softw are Trigger -- 0001b 0010b Timer A0 -- 0011b Timer A1 -- 0100b Timer A2 -- 0101b -- -- _____ 0110b -- Tw o Edges of INT0 Pin 0111b Timer B0 -- -- 1000b Timer B1 -- 1001b Timer B2 -- 1010b UART0 Transmit -- UART0 Receive 1011b -- 1100b UART2 Transmit -- 1101b UART2 Receive -- 1110b A/D Conversion UART1 Transmit -- 1111b
Figure 13.2
DM0SL Register
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13. DMAC
DMA1 Request Factor Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address 03BAh DM1SL Bit Name Bit Symbol DSEL0 DMA Request factor Select Bit (NOTE 1) DSEL1 DSEL2 DSEL3 Nothing is assigned. When w rite, set to "0". -- When read, their contents are "0". (b5-b4) DMS
After Reset 00h Function
RW RW RW RW RW -- RW
DMA Request Factor Expansion 0: Basic factor of request Select Bit 1: Extended factor of request Softw are DMA Request Bit A DMA request is generated by setting this bit to "1" w hen the DMS bit is "0" (basic factor) and the DSEL3 to DSEL0 bits are "0001b" (softw are trigger). The value of this bit w hen read is "0".
DSR
RW
NOTES : 1. The factors of DMA1 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the manner described below . DSEL3 to DSEL0 DMS=0(Basic Factor of Request) DMS=1(Extended Factor of Request) _____ -- 0000b Falling Edge of INT1 Pin 0001b Softw are Trigger -- 0010b Timer A0 -- 0011b Timer A1 -- 0100b Timer A2 -- 0101b -- -- 0110b -- -- 0111b 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b Timer B0 Timer B1 Timer B2 UART0 Transmit UART0 Receive/ACK0 UART2 Transmit UART2 Receive/ACK2 A/D Conversion UART1 Receive/ACK1
_____
Tw o Edges of INT1 Pin -- -- -- -- -- -- -- --
Figure 13.3
DM1SL Register
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13. DMAC
DMAi Control Register (i=0,1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DM0CON DM1CON Bit Symbol DMBIT DMASL DMAS DMAE DSD DAD -- (b7-b6)
Address 002Ch 003Ch Bit Name Transfer Unit Bit Select Bit Repeat Transfer Mode Select Bit DMA Request Bit DMA Enable Bit Source Address Direction Select Bit (2) Destination Address Direction Select Bit (2)
After Reset 00000X00b 00000X00b Function 0 : 16 bits 1 : 8 bits 0 : Single transfer 1 : Repeat transfer 0 : DMA not requested 1 : DMA requested 0 : Disabled 1 : Enabled 0 : Fixed 1 : Forw ard 0 : Fixed 1 : Forw ard
RW RW RW RW(1) RW RW RW --
Nothing is assigned. When w rite, set to "0". When read, their contents are "0".
NOTES : 1. The DMAS bit can be set to "0" by w riting "0" in a program (This bit remains unchanged even if "1" is w ritten). 2. At least one of the DAD and DSD bits must be "0" (address direction fixed).
Figure 13.4
DM0CON and DM1CON Register
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13. DMAC
DMAi Source Pointer (i = 0, 1) (1)
(b23) b7 (b19) b3 (b16) (b15) b0 b7 (b8) b0 b7 b0
Symbol SAR0 SAR1 Function Set the source address of transfer Nothing is assigned. When w rite, set "0". When read, their contents are "0".
Address 0022h to 0020h 0032h to 0030h
After Reset Indeterminate Indeterminate Setting Range 00000h to FFFFFh RW RW --
NOTES : 1. If the DSD bit in the DMiCON register is "0" (fixed), this register can only be w ritten to w hen the DMAE bit in the DMiCON register is "0" (DMA disabled). If the DSD bit is "1" (forw ard direction), this register can be w ritten to at any time. If the DSD bit is "1" and the DMAE bit is "1" (DMA enabled), the DMAi forw ard address pointer can be read from this register. Otherw ise, the value w ritten to it can be read.
DMAi Destination Pointer (i = 0, 1) (1)
(b23) b7 (b19) b3 (b16) (b15) b0 b7 (b8) b0 b7 b0
Symbol DAR0 DAR1 Function Set the destination address of transfer Nothing is assigned. When w rite, set "0". When read, their contents are "0".
Address 0026h to 0024h 0036h to 0034h
After Reset Indeterminate Indeterminate Setting Range 00000h to FFFFFh RW RW --
NOTES : 1. If the DAD bit in the DMiCON register is "0" (fixed), this register can only be w ritten to w hen the DMAE bit in the DMiCON register is "0"(DMA disabled). If the DAD bit is "1" (forw ard direction), this register can be w ritten to at any time. If the DAD bit is "1" and the DMAE bit is "1" (DMA enabled), the DMAi forw ard address pointer can be read from this register. Otherw ise, the value w ritten to it can be read.
DMAi Transfer Counter (i = 0, 1)
(b15) b7 (b8) b0 b7 b0
Symbol TCR0 TCR1 Function
Address 0029h to 0028h 0039h to 0038h
After Reset Indeterminate Indeterminate Setting Range 0000h to FFFFh RW
Set the transfer count minus 1. The w ritten value is stored in the DMAi transfer counter reload register, and w hen the DMAE bit in the DMiCON register is set to "1" (DMA enabled) or the DMAi transfer counter underflow s w hen the DMASL bit in the DMiCON register is "1" (repeat transfer), the value of the DMAi transfer counter reload register is transferred to the DMAi transfer counter. When read, the DMAi transfer counter is read.
RW
Figure 13.5
SAR0, SAR1, DAR0, DAR1, TCR0 and TCR1 Registers
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13. DMAC
13.1
Transfer Cycles
The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination write) bus cycle. The number of read and write bus cycles is affected by the source and destination addresses of transfer. During memory extension and microprocessor modes, it is also affected by the BYTE pin level. Furthermore, the bus cycle itself is extended by a software wait or RDY signal.
13.1.1
Effect of Source and Destination Addresses
If the transfer unit and data bus both are 16 bits and the source address of transfer begins with an odd address, the source read cycle consists of one more bus cycle than when the source address of transfer begins with an even address. Similarly, if the transfer unit and data bus both are 16 bits and the destination address of transfer begins with an odd address, the destination write cycle consists of one more bus cycle than when the destination address of transfer begins with an even address.
13.1.2
Effect of BYTE Pin Level
During memory extension and microprocessor modes, if 16 bits of data are to be transferred on an 8-bit data bus (input on the BYTE pin = high), the operation is accomplished by transferring 8 bits of data twice. Therefore, this operation requires two bus cycles to read data and two bus cycles to write data. Furthermore, if the DMAC is to access the internal area (internal ROM, internal RAM, or SFR), unlike in the case of the CPU, the DMAC does it through the data bus width selected by the BYTE pin.
13.1.3
Effect of Software Wait
For memory or SFR accesses in which one or more software wait states are inserted, the number of bus cycles required for that access increases by an amount equal to software wait states.
13.1.4
Effect of RDY Signal
During memory extension and microprocessor modes, DMA transfers to and from an external area are affected by the RDY signal. Refer to 7.2.6 RDY Signal. Figure 13.6 shows the example of the Transfer Cycles for Source Read. For convenience, the destination write cycle is shown as one cycle and the source read cycles for the different conditions are shown. In reality, the destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle changing accordingly. When calculating transfer cycles, take into consideration each condition for the source read and the destination write cycle, respectively. For example, when data is transferred in 16 bit units using an 8-bit bus ((2) on Figure 13.6), two source read bus cycles and two destination write bus cycles are required.
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13. DMAC
(1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address
BCLK Address bus RD signal WR signal Data bus
Dummy cycle Dummy cycle
CPU use
Source
Destination
CPU use
CPU use
Source
Destination
CPU use
(2) When the transfer unit is 16 bits and the source address of transfer is an odd address, or when the transfer unit is 16 bits and an 8-bit bus is used
BCLK Address bus RD signal WR signal Data bus
CPU use Source Source + 1 Destination Dummy cycle CPU use CPU use Source Source + 1 Destination Dummy cycle CPU use
(3) When the source read cycle under condition (1) has one wait state inserted
BCLK Address bus RD signal WR signal Data bus
Destination Dummy cycle CPU use Source Destination Dummy cycle CPU use
CPU use
Source
CPU use
(4) When the source read cycle under condition (2) has one wait state inserted
BCLK Address bus RD signal WR signal Data bus
CPU use Source Source + 1 Destination Dummy cycle CPU use CPU use Source Source + 1 Destination Dummy cycle CPU use
NOTES : 1. The same timing changes occur with the respective conditions at the destination as at the source.
Figure 13.6
Transfer Cycles for Source Read
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13. DMAC
13.2
DMA Transfer Cycles
Any combination of even or odd transfer read and write addresses is possible. Table 13.2 lists the DMA Transfer Cycles. Table 13.3 lists the Coefficient j, k. The number of DMAC transfer cycles can be calculated as follows: No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k Table 13.2 DMA Transfer Cycles
Transfer Unit 8-bit Transfers (DMBIT= 1)
Bus Width 16-bit (BYTE= L) 8-bit (BYTE = H)
Access Address Even Odd Even Odd Even Odd Even Odd
Single-Chip Mode No. of Read No. of Write Cycles Cycles 1 1 1 1 -- -- -- -- 1 1 2 2 -- -- -- --
16-bit Transfers 16-bit (DMBIT= 0) (BYTE = L) 8-bit (BYTE = H) -- : This condition does not exist.
Table 13.3 Coefficient j, k
Memory Expansion Mode Microprocessor Mode No. of Read No. of Write Cycles Cycles 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2
j k
Internal Area Internal ROM, RAM No Wait With Wait 1 2 1 2
SFR 1-Wait 2 2
External Area Separate Bus No Wait 1-Wait 1 2 2 2
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13. DMAC
13.3
DMA Enable
When a data transfer starts after setting the DMAE bit in the DMiCON register (i = 0, 1) to "1" (enabled), the DMAC operates as follows: (1) Reload the forward address pointer with the SARi register value when the DSD bit in the DMiCON register is "1" (forward) or the DARi register value when the DAD bit in the DMiCON register is "1" (forward). (2) Reload the DMAi transfer counter with the DMAi transfer counter reload register value. If the DMAE bit is set to "1" again while it remains set, the DMAC performs the above operation. However, if a DMA request may occur simultaneously when the DMAE bit is being written, follow the steps below. Step 1: Write "1" to the DMAE bit and DMAS bit in the DMiCON register simultaneously. Step 2: Make sure that the DMAi is in an initial state as described above (1) and (2) in a program. If the DMAi is not in an initial state, the above steps should be repeated.
13.4
DMA Request
The DMAC can generate a DMA request as triggered by the factor of request that is selected with the DMS and DSEL3 to DSEL0 bits in the DMiSL register (i = 0, 1) on either channel. Table 13.4 lists the Timing at Which the DMAS Bit Changes State. Whenever a DMA request is generated, the DMAS bit is set to "1" (DMA requested) regardless of whether or not the DMAE bit is set. If the DMAE bit was set to "1" (enabled) when this occurred, the DMAS bit is set to "0" (DMA not requested) immediately before a data transfer starts. This bit cannot be set to "1" in a program (it can only be set to "0"). The DMAS bit may be set to "1" when the DMS or the DSEL3 to DSEL0 bits change state. Therefore, always be sure to set the DMAS bit to "0" after changing the DMS or the DSEL3 to DSEL0 bits. Because if the DMAE bit is "1", a data transfer starts immediately after a DMA request is generated, the DMAS bit in almost all cases is "0" when read in a program. Read the DMAE bit to determine whether the DMAC is enabled. Table 13.4 Timing at Which the DMAS Bit Changes State
DMA Factor Software Trigger Peripheral Function
DMAS Bit of the DMiCON Register Timing at which the bit is set to "1" Timing at which the bit is set to "0" When the DSR bit in the DMiSL register * Immediately before a data transfer starts is set to "1" * When set by writing "0" in a program When the interrupt control register for the peripheral function that is selected by the DSEL3 to DSEL0 and DMS bits in the DMiSL register has its IR bit set to "1"
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13.5
Channel Priority and DMA Transfer Timing
If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are detected active in the same sampling period (one period from a falling edge to the next falling edge of BCLK), the DMAS bit on each channel is set to "1" (DMA requested) at the same time. In this case, the DMA requests are arbitrated according to the channel priority, DMA0 > DMA1. The following describes DMAC operation when DMA0 and DMA1 requests are detected active in the same sampling period. Figure 13.7 shows an example of DMA Transfer by External Factors. DMA0 request having priority is received first to start a transfer when a DMA0 request and DMA1 request are generated simultaneously. After one DMA0 transfer is completed, a bus arbitration is returned to the CPU. When the CPU has completed one bus access, a DMA1 transfer starts. After one DMA1 transfer is completed, the bus arbitration is again returned to the CPU. In addition, DMA requests cannot be counted up since each channel has one DMAS bit. Therefore, when DMA requests, as DMA1 in Figure 13.7, occurs more than one time, the DMAS bit is set to "0" as soon as getting the bus arbitration. The bus arbitration is returned to the CPU when one transfer is completed. Refer to 7.2.7 HOLD Signal for details about bus arbitration between the CPU and DMA.
An example where DMA requests for external factors are detected active at the same
BCLK
DMA0 DMA1 CPU INT0 DMA0 request bit INT1 DMA1 request bit
Figure 13.7 DMA Transfer by External Factors
Bus arbitration
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14. Timers
Six 16-bit timers, each capable of operating independently of the others, can be classified by function as either Timer A (three) and Timer B (three). The count source for each timer acts as a clock, to control such timer operations as counting, reloading, etc. Figures 14.1 and 14.2 show block diagrams of Timer A and Timer B configuration, respectively.
f2 PCLK0 bit =0
1/2 * Main clock
f1 PCLK0 bit =1
f1 or f2 XCIN f8 f32
Clock prescaler
1/32
Reset
fC32
1/8 1/4
f1 or f2 f8 f32 fC32
Set the CPSR bit in the CPSRF register to "1" (= prescaler reset)
00 01 10 11
TCK1 to TCK0
00: Timer mode 10: One-shot timer mode 11: PWM mode
TMOD1 to TMOD0
Timer A0 interrupt
TA0IN
Noise filter
01 00
Timer A0
01: Event counter mode
11 TA0TGH to TA0TGL TCK1 to TCK0
00 01 10 11
00: Timer mode 10: One-shot timer mode 11: PWM mode
10 TMOD1 to TMOD0
Timer A1 interrupt
TA1IN
Noise filter
01 00 11
Timer A1
01: Event counter mode
TA1TGH to TA1TGL
00 01 10 11
TCK1 to TCK0
00: Timer mode 10: One-shot timer mode 11: PWM mode
10 TMOD1 to TMOD0
Timer A2 interrupt
TA2IN
Noise filter
01 00 11
Timer A2
01: Event counter mode
TA2TGH to TA2TGL
Timer B2 overflow or underflow TCK1 to TCK0, TMOD1 to TMOD0 : Bits in TAiMR register (i=0 to 2) TAiGH to TAiGL: Bits in ONSF register and TRGSR register
Figure 14.1
Timer A Configuration
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f2
PCLK0 bit =0 Clock prescaler f1 or f2 XCIN PCLK0 bit =1
1/2 * Main clock
f1
1/32
Reset
fC32
1/8 1/4
f8 f32
Set the CPSR bit in the CPSRF register to "1" (= prescaler reset)
f1 or f2 f8 f32 fC32
00 01 10 11
Timer B2 overflow or underflow (to a count source of the timer A)
TCK1 to TCK0
00: Timer mode 10: Pulse period / pulse width measurement mode
TMOD1 to TMOD0 Noise filter 1 0 TCK1
Timer B0 interrupt
Timer B0
01: Event counter mode 00: Timer mode 10: Pulse period / pulse width measurement mode
TMOD1 to TMOD0
TB0IN
00 01 10 11
TCK1 to TCK0
Timer B1 interrupt
TB1IN
00 01 10 11
Noise filter TCK1 to TCK0
1 0 TCK1
Timer B1
01: Event counter mode 00: Timer mode 10: Pulse period / pulse width measurement mode
TMOD1 to TMOD0
Timer B2 interrupt
TB2IN
Noise filter TCK1 to TCK0
1 0 TCK1
Timer B2
01: Event counter mode
TCK1 to TCK0, TMOD1 to TMOD0 : Bits in TBiMR register (i=0 to 2)
Figure 14.2
Timer B Configuration
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14.1
Timer A
Figure 14.3 shows a Timer A Block Diagram. Figures 14.4 to 14.6 show registers related to the Timer A. The Timer A supports the following four modes. Except in event counter mode, Timers A0 to A2 all have the same function. Use the TMOD1 to TMOD0 bits in the TAiMR register (i = 0 to 2) to select the desired mode. * Timer Mode: The timer counts an internal count source. * Event Counter Mode: The timer counts pulses from an external device or overflows and underflows of other timers. * One-shot Timer Mode: The timer outputs a pulse only once before it reaches the minimum count "0000h". * Pulse Width Modulation (PWM) Mode: The timer outputs pulses in a given width successively.
Select clock
High-Order Bits of Data Bus Low-Order Bits of Data Bus 8 low-order bits Reload Register 8 high-order bits
Select Count Source f1 or f2 01 f8 10 f32 fC32 11
TCK1 to TCK0 00
* Timer : TMOD1 to TMOD0=00, MR2=0 * One-Shot Timer : TMOD1 to TMOD0=10 TMOD1 to TMOD0, * Pulse Width Modulation : TMOD1 to TMOD0=11 MR2 * Timer(gate function) : TMOD1 to TMOD0=00, MR2=1 * Event counter : TMOD1 to TMOD0=01
TAiIN
Polarity Selector
00
TAiS
Counter Increment / decrement Always decrement except in event counter mode
TB2 Overflow (1) TAj Overflow (1) TAk Overflow (1)
01 10 11 TAiTGH to TAiTGL
00 To external 01 trigger circuit 11 Decrement 01
TAiUD
0 1
TMOD1 to TMOD0
Pulse Output
MR2
TAiOUT Toggle Flip Flop i=0 to 2 j=i-1, however, do not set when i=0 k=i+1, however, do not set when i=2 NOTES: 1. Overflow or underflow TCK1 to TCK0, TMOD1 to TMOC0, MR2 to MR1 : Bits in TAiMR register TAiTGH to TAiTGL : Bits in ONSF register if i=0 or bits in TRGSR register if i=1 to 2 TAiS : Bits in the TABSR register TAiUD : Bits in the UDF register
Figure 14.3
Timer A Block Diagram
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Timer Ai Mode Register (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address 0396h to 0398h TA0MR to TA2MR Bit Name Bit Symbol Operation Mode Select Bit TMOD0
After Reset 00h Function
b1 b0
RW RW
TMOD1 MR0 MR1 MR2 MR3 TCK0 TCK1 --
0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot timer mode 1 1 : Pulse w idth modulation (PWM) mode Function varies w ith each operation mode
RW RW RW RW RW RW RW
Count Source Select Bit
Function varies w ith each operation mode
Timer Ai Register (i= 0 to 2) (1)
(b15) b7 (b8) b0 b7 b0
Symbol TA0 TA1 TA2 Mode Timer Mode Event Counter Mode One-Shot Timer Mode Pulse Width Modulation Mode (16-Bit PWM) Pulse Width Modulation Mode (8-Bit PWM)
Address 0387h, 0386h 0389h, 0388h 038Bh, 038Ah Function
After Reset Indeterminate Indeterminate Indeterminate Setting Range 0000h to FFFFh 0000h to FFFFh RW 0000h to FFFFh(2, 4) 0000h to FFFEh
(3, 4)
RW RW
Divide the count source by n + 1 w here n = set value Divide the count source by FFFFh - n + 1 w here n = set value w hen counting up or by n + 1 w hen counting dow n (5) Divide the count source by n w here n = set value and factor the timer to stop Modify the pulse w idth as follow s: PWM period: (216 - 1) / fj High level PWM pulse w idth: n / fj w here n = set value, fj = count source frequency Modify the pulse w idth as follow s: PWM period: (28 - 1) x (m + 1)/ fj High level PWM pulse w idth: (m + 1)n / fj w here n = high-order address set value, m = low -order address set value, fj = count source frequency
WO
WO
00h to FEh (High-order address) 00h to FFh (Low -order address)
(3, 4)
WO
NOTES : 1. The register must be accessed in 16-bit units. 2. If the TAi register is set to "0000h," the counter does not w ork and timer Ai interrupt requests are not generated either. Furthermore, if "pulse output" is selected, no pulses are output from the TAiOUT pin. 3. If the TAi register is set to "0000h," the pulse w idth modulator does not w ork, the output level on the TAiOUT pin remains low , and timer Ai interrupt requests are not generated either. The same applies w hen the 8 high-order bits of the timer TAi register are set to "00h" w hile operating as an 8-bit pulse w idth modulator. 4. Use the MOV instruction to w rite to the TAi register. 5. The timer counts pulses from an external device or overflow s or underflow s in other timers.
Figure 14.4
TAiMR and TAi Registers
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Count Start Flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TABSR Bit Symbol TA0S TA1S TA2S -- (b4-b3) TB0S TB1S TB2S
Address After Reset 0380h 000XX000b Bit Name Function 0 : Stops counting Timer A0 Count Start Flag 1 : Starts counting Timer A1 Count Start Flag Timer A2 Count Start Flag Nothing is assigned. When w rite, set to "0". When read, their contents are indeterminate. Timer B0 Count Start Flag Timer B1 Count Start Flag Timer B2 Count Start Flag 0 : Stops counting 1 : Starts counting
RW RW RW RW -- RW RW RW
Up/Down Flag (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UDF Bit Symbol TA0UD TA1UD TA2UD -- (b4-b3)
Address 0384h Bit Name Timer A0 Up/Dow n Flag Timer A1 Up/Dow n Flag Timer A2 Up/Dow n Flag
After Reset XX0XX000b Function 0 : Dow n count 1 : Up count Enabled by setting the MR2 bit in the TAiMR register to "0" (= sw itching source in UDF register) during event counter mode.
RW RW RW RW --
Nothing is assigned. When w rite, set to "0". When read, their contents are indeterminate. Timer A2 Tw o-Phase Pulse Signal Processing Select Bit 0 : Tw o-phase pulse signal processing disabled 1 : Tw o-phase pulse signal processing enabled (2, 3)
TA2P
WO
-- (b7-b6)
Nothing is assigned. When w rite, set to "0". When read, their contents are indeterminate.
--
NOTES : 1. Use MOV instruction to w rite to this register. 2. Make sure the port direction bits for the TA2IN and TA2OUT pins are set to "0" (input mode). 3. When not using the tw o-phase pulse signal processing function, set the bit corresponding to timer A2 to "0".
Figure 14.5
TABSR and UDF Registers
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One-Shot Start Flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol ONSF Bit Symbol TA0OS TA1OS TA2OS -- (b5-b3) TA0TGL
Address 0382h Bit Name Timer A0 One-Shot Start Flag Timer A1 One-Shot Start Flag Timer A2 One-Shot Start Flag
After Reset 00XXX000b Function The timer starts counting by setting this bit to "1" w hile the TMOD1 to TMOD0 bits in the TAiMR register i = 0 to 2) = 10b (= one-shot timer mode) and the MR2 bit in the TAiMR register = 0 (=TAiOS bit enabled). When read, its content is 0". RW RW RW RW --
Nothing is assigned. When w rite, set to "0". When read, their contents are indeterminate. Timer A0 Event/Trigger Select Bit
b7 b6
TA0TGH
0 0 : Input on TA0IN is selected (1) 0 1 : TB2 is selected (2) 1 0 : Do not set 1 1 : TA1 is selected (2)
RW
RW
NOTES : 1. Make sure the PD7_1 bit in the PD7 register is set to "0" (= input mode). 2. Overflow or underflow .
Trigger Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRGSR Bit Symbol TA1TGL
Address 0383h Bit Name Timer A1 Event/Trigger Select Bit
b1 b0
After Reset XXXX0000b Function 0 0 : Input on TA1IN is selected (1) 0 1 : TB2 is selected (2) 1 0 : TA0 is selected (2) 1 1 : TA2 is selected (2) RW RW
TA1TGH Timer A2 Event/Trigger Select Bit TA2TGL
RW
b3 b2
TA2TGH -- (b7-b4)
0 0 : Input on TA2IN is selected (1) 0 1 : TB2 is selected (2) 1 0 : TA1 is selected (2) 1 1 : Do not set Nothing is assigned. When w rite, set to "0". When read, their contents are indeterminate.
RW
RW
--
NOTES : 1. Make sure the port direction bits for the TA1IN to TA2IN pins are set to "0" (= input mode). 2. Overflow or underflow .
Figure 14.6
ONSF and TRGSR Registers
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Clock Prescaler Reset Flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol CPSRF Bit Symbol -- (b6-b0) CPSR
Address 0381h Bit Name Nothing is assigned. When w rite, set to "0". When read, their contents are indeterminate. Clock Prescaler Reset Flag
After Reset 0XXXXXXXb Function RW --
Setting this bit to "1" initializes the prescaler for the timekeeping clock. (When read, its content is "0".)
RW
Figure 14.7
CPSRF Register
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14.1.1
Timer Mode
In timer mode, the timer counts a count source generated internally (see Table 14.1). Figure 14.8 shows TAiMR Register in Timer Mode. Table 14.1 Specifications in Timer Mode
Item Count source Count Operation
Divide Ratio Count Start Condition Count Stop Condition Interrupt Request Generation Timing TAiIN Pin Function TAiOUT Pin Function Read from Timer Write to Timer
Specification f1, f2, f8, f32, fC32 * Down-count * When the timer underflows, it reloads the reload register contents and continues counting 1/(n+1) n: set value of TAi register (i= 0 to 2) 0000h to FFFFh Set TAiS bit in TABSR register to "1" (= start counting) Set TAiS bit to "0" (= stop counting) Timer underflow I/O port or gate input I/O port or pulse output Count value can be read by reading TAi register * When not counting and until the 1st count source is input after counting start Value written to TAi register is written to both reload register and counter * When counting (after 1st count source input) Value written to TAi register is written to only reload register (Transferred to counter when reloaded next) * Gate function Counting can be started and stopped by an input signal to TAiIN pin * Pulse output function Whenever the timer underflows, the output polarity of TAiOUT pin is inverted. When TAiS bit is set to "0" (stop counting), the pin outputs a low.
Select Function
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Timer Ai Mode Register (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
0
00
Address Symbol 0396h to 0398h TA0MR to TA2MR Bit Name Bit Symbol TMOD0 Operation Mode Select Bit TMOD1 Pulse Output Function Select Bit MR0
After Reset 00h Function
b1 b0
0 0 : Timer mode 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (1) (TAiOUT pin is a pulse output pin)
b4 b3
RW RW RW
RW
Gate Function Select Bit MR1
MR2
0 0 : Gate function not available 0 1 : (TAiIN pin functions as I/O port) 1 0 : Counts w hile input on the TAiIN pin is low (2) 1 1 : Counts w hile input on the TAiIN pin is high (2) Set to "0" in timer mode Count Source Select Bit
RW
RW
MR3 TCK0
RW
b7 b6
TCK1 NOTES : 1. TA0OUT pin is N-channel open drain output. 2. The port direction bit for the TAiIN pin is set to "0" (= input mode). 3. Selected by PCLK0 bit in the PCLKR register.
0 0 : f1 or f2 (3) 0 1 : f8 1 0 : f32 1 1 : fC32
RW
RW
Figure 14.8
TAiMR Register in Timer Mode
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14.1.2
Event Counter Mode
In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers. Timer A2 can count two-phase external signals. Table 14.2 lists Specifications in Event Counter Mode (when not processing two-phase pulse signal). Figure 14.9 shows TAiMR Register in Event Counter Mode (when not using two-phase pulse signal processing). Table 14.2 Specifications in Event Counter Mode (when not processing two-phase pulse signal)
Item Count Source
Count Operation
Divided Ratio Count Start Condition Count Stop Condition Interrupt Request Generation Timing TAiIN Pin Function TAiOUT Pin Function Read from Timer Write to Timer
Specification * External signals input to TAiIN pin (i=0 to 2) (effective edge can be selected in program) * Timer B2 overflows or underflows, Timer Aj (j=i-1, however, do not set when i=0) overflows or underflows, Timer Ak (k=i+1, however, do not set when i=2) overflows or underflows * Up-count or down-count can be selected by external signal or program * When the timer overflows or underflows, it reloads the reload register contents and continues counting. When operating in free-running mode, the timer continues counting without reloading. 1/ (FFFFh - n + 1) for up-count 1/ (n + 1) for down-count n : set value of TAi register 0000h to FFFFh Set TAiS bit in the TABSR register to "1" (= start counting) Set TAiS bit to "0" (= stop counting) Timer overflow or underflow I/O port or count source input I/O port, pulse output, or up/down-count select input Count value can be read by reading TAi register * When not counting and until the 1st count source is input after counting start Value written to TAi register is written to both reload register and counter * When counting (after 1st count source input) Value written to TAi register is written to only reload register (Transferred to counter when reloaded next) * Free-run count function Even when the timer overflows or underflows, the reload register content is not reloaded to it * Pulse output function Whenever the timer underflows or underflows, the output polarity of TAiOUT pin is inverted. When TAiS bit is set to "0" (stop counting), the pin outputs a low.
Select Function
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Timer Ai Mode Register (i=0 to 2) (when not using two-phase pulse signal processing)
b7 b6 b5 b4 b3 b2 b1 b0
0
01
Address Symbol 0396h to 0398h TA0MR to TA2MR Bit Name Bit Symbol TMOD0 Operation Mode Select Bit TMOD1 Pulse Output Function Select Bit MR0
After Reset 00h Function
b1 b0
0 1 : Event counter mode (1) 0 : Pulse is not output (TAiOUT pin functions as I/O port) 1 : Pulse is output (2) (TAiOUT pin functions as pulse output pin) 0 : Counts falling edge of external signal 1 : Counts rising edge of external signal 0 : UDF register 1 : Input signal to TAiOUT pin (4)
RW RW RW
RW
MR1 MR2 MR3 TCK0
Count Polarity Select Bit (3) Up/Dow n Sw itching Factor Select Bit
RW RW RW RW
Set to "0" in event counter mode Count Operation Type Select Bit 0 : Reload type 1 : Free-run type
Can be "0" or "1" w hen not using tw o-phase pulse signal processing TCK1 RW NOTES : 1. During event counter mode, the count source can be selected using the ONSF and TRGSR registers. 2. TA0OUT pin is N-channel open drain output. 3. Effective w hen the TAiTGH and TAiTGL bits in the ONSF or TRGSR register are "00b" (TAiIN pin input). 4. Count dow n w hen input on TAiOUT pin is low or count up w hen input on that pin is high. The port direction bit for TAiOUT pin is set to "0" (= input mode).
Figure 14.9
TAiMR Register in Event Counter Mode (when not using two-phase pulse signal processing)
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Table 14.3 lists Specifications in Event Counter Mode (when processing two-phase pulse signal with Timer A2). Figure 14.10 shows TA2MR Register in Event Counter Mode (when using two-phase pulse signal processing with Timer A2). Table 14.3 Specifications in Event Counter Mode (when processing two-phase pulse signal with Timer A2)
Item Count Source Count Operation
Divide Ratio Count Start Condition Count Stop Condition Interrupt Request Generation Timing TA2IN Pin Function TA2OUT Pin Function Read from Timer Write to Timer
Specification * Two-phase pulse signals input to TA2IN or TA2OUT pins * Up-count or down-count can be selected by two-phase pulse signal * When the timer overflows or underflows, it reloads the reload register contents and continues counting. When operating in free-running mode, the timer continues counting without reloading. 1/ (FFFFh - n + 1) for up-count 1/ (n + 1) for down-count n : set value of TA2 register 0000h to FFFFh Set TA2S bit of TABSR register to "1" (= start counting) Set TA2S bit to "0" (= stop counting) Timer overflow or underflow Two-phase pulse input Two-phase pulse input Count value can be read by reading Timer A2 register * When not counting and until the 1st count source is input after counting start Value written to TA2 register is written to both reload register and counter * When counting (after 1st count source input) Value written to TA2 register is written to reload register (Transferred to counter when reloaded next) * The timer counts up rising edges or counts down falling edges on TA2IN pin when input signals on TA2OUT pin is "H".
Select Function
TA2OUT TA2IN
Upcount Upcount Upcount Downcount Downcount Downcount
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Timer A2 Mode Register (when using two-phase pulse signal processing)
b7 b6 b5 b4 b3 b2 b1 b0
0
010001
Address After Reset Symbol 0398h 00h TA2MR Bit Name Bit Symbol Function Operation Mode Select Bit TMOD0 b1 b0 0 1 : Event counter mode TMOD1 MR0 To use tw o-phase pulse signal processing, set this bit to "0". To use tw o-phase pulse signal processing, set this bit to "0". MR1 To use tw o-phase pulse signal processing, set this bit to "1". MR2 MR3 To use tw o-phase pulse signal processing, set this bit to "0". Count Operation Type Select Bit 0 : Reload type TCK0 1 : Free-run type TCK1 To use tw o-phase pulse signal processing, set this bit to "0". (1)
RW RW RW RW RW RW RW RW RW
NOTES : 1. If tw o-phase pulse signal processing is desired, follow ing register settings are required: * Set the TA2P bit in the UDF register to "1" (tw o-phase pulse signal processing function enabled). * Set the TA2TGH and TA2TGL bits in the TRGSR register to "00b" (TA2IN pin input). * Set the port direction bits for TA2IN and TA2OUT to "0" (input mode).
Figure 14.10
TA2MR Register in Event Counter Mode (when using two-phase pulse signal processing with Timer A2)
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14.1.3
One-shot Timer Mode
In one-shot timer mode, the timer is activated only once by one trigger (see Table 14.4). When the trigger occurs, the timer starts up and continues operating for a given period. Figure 14.11 shows the TAiMR Register in One-Shot Timer Mode. Table 14.4 Specifications in One-shot Timer Mode
Item Count Source Count Operation
Divide Ratio Count start Condition
Count Stop Condition Interrupt Request Generation Timing TAiIN Pin Function TAiOUT Pin Function Read from Timer Write to Timer
Specification f1, f2, f8, f32, fC32 * Down-count * When the counter reaches 0000h, it stops counting after reloading a new value * If a trigger occurs when counting, the timer reloads a new count and restarts counting 1/n n : set value of TAi register (i=0 to 2) 0000h to FFFFh However, the counter does not work if the divide-by-n value is set to 0000h. TAiS bit in the TABSR register = 1 (start counting) and one of the following triggers occurs. * External trigger input from the TAiIN pin * Timer B2 overflow or underflow, Timer Aj (j=i-1, however, do not set when i=0) overflow or underflow, Timer Ak (k=i+1, however, do not set when i=2) overflow or underflow * The TAiOS bit in the ONSF register is set to "1"(= timer starts) * When the counter is reloaded after reaching "0000h" * TAiS bit is set to "0" (= stop counting) When the counter reaches "0000h" I/O port or trigger input I/O port or pulse output An indeterminate value is read by reading TAi register * When not counting and until the 1st count source is input after counting start Value written to TAi register is written to both reload register and counter * When counting (after 1st count source input) Value written to TAi register is written to only reload register (Transferred to counter when reloaded next) * Pulse output function The timer outputs a low when not counting and a high when counting.
Select Function
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Timer Ai Mode Register (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
0
10
Symbol Address After Reset 0396h to 0398h 00h TA0MR to TA2MR Bit Name Bit Symbol Function TMOD0 Operation Mode Select Bit b1 b0 1 0 : One-shot timer mode TMOD1 Pulse Output Function Select 0 : Pulse is not output Bit (TAiOUT pin functions as I/O port) MR0 1 : Pulse is output (1) (TAiOUT pin functions as a pulse output pin) MR1 External Trigger Select Bit (2) Trigger Select Bit 0 : Falling edge of input signal to TAiIN pin (3) 1 : Rising edge of input signal to TAiIN pin (3) 0 : TAiOS bit is enabled 1 : Selected by TAiTGH to TAiTGL bits
RW RW RW
RW
RW
MR2 MR3 TCK0
RW RW RW
TCK1
Set to "0" in one-shot timer mode Count Source Select Bit b7 b6 0 0 : f1 or f2 (4) 0 1 : f8 1 0 : f32 1 1 : fC32
RW
NOTES : 1. TA0OUT pin is N-channel open drain output. 2. Effective w hen the TAiTGH and TAiTGL bits in the ONSF or TRGSR register are "00b" (TAiIN pin input). 3. The port direction bit for the TAiIN pin is set to "0" (= input mode). 4. Selected by PCLK0 bit in the PCLKR register.
Figure 14.11
TAiMR Register in One-Shot Timer Mode
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M16C/30P Group
14. Timers
14.1.4
Pulse Width Modulation (PWM) Mode
In PWM mode, the timer outputs pulses of a given width in succession (see Table 14.5). The counter functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. Figure 14.12 shows TAiMR Register in PWM Mode. Figures 14.13 and 14.14 show Example of 16-bit Pulse Width Modulator Operation and Example of 8-bit Pulse Width Modulator Operation. Table 14.5 Specifications in PWM Mode
Item Count Source Count Operation
16-bit PWM 8-bit PWM Count Start Condition
Count Stop Condition Interrupt Request Generation Timing TAiIN Pin Function TAiOUT Pin Function Read from Timer Write to Timer
Specification f1, f2, f8, f32, fC32 * Down-count (operating as an 8-bit or a 16-bit pulse width modulator) * The timer reloads a new value at a rising edge of PWM pulse and continues counting * The timer is not affected by a trigger that occurs during counting * High level width n / fj n : set value of TAi register (i=o to 2) 16-1) / fj fixed * Cycle time (2 fj: count source frequency (f1, f2, f8, f32, fC32) * High level width n x (m+1) / fj n : set value of TAi register high-order address * Cycle time (28-1) x (m+1) / fj m : set value of TAi register low-order address * TAiS bit of TABSR register is set to "1" (= start counting) * The TAiS bit = 1 and external trigger input from the TAiIN pin * The TAiS bit = 1 and one of the following external triggers occurs * Timer B2 overflow or underflow, Timer Aj (j=i-1, however, do not set when i=0) overflow or underflow, Timer Ak (k=i+1, however, do not set when i=2) overflow or underflow TAiS bit is set to "0" (= stop counting) PWM pulse goes "L" I/O port or trigger input Pulse output An indeterminate value is read by reading TAi register * When not counting and until the 1st count source is input after counting start Value written to TAi register is written to both reload register and counter * When counting (after 1st count source input) Value written to TAi register is written to only reload register (Transferred to counter when reloaded next)
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14. Timers
Timer Ai Mode Register (i= 0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
11
Symbol Address 0396h to 0398h TA0MR to TA2MR Bit Name Bit Symbol Operation Mode Select Bit TMOD0 TMOD1 Pulse Output Function Select Bit MR0
After Reset 00h Function
b1 b0
1 1 : PWM mode (1) 0 : Pulse is not output (TAiOUT pin functions as I/O port) 1 : Pulse is output (4) (TAiOUT pin functions as a pulse output pin) 0 : Falling edge of input signal to TAiIN pin (3) 1 : Rising edge of input signal to TAiIN pin (3) 0 : Write "1" to TAiS bit in the TASF register 1 : Selected by TAiTGH to TAiTGL bits 0 : Functions as a 16-bit pulse w idth modulator 1 : Functions as an 8-bit pulse w idth modulator
b7 b6
RW RW RW
RW
MR1
External Trigger Select Bit (2) Trigger Select Bit
RW
MR2 16/8-Bit PWM Mode Select Bit Count Source Select Bit TCK0
RW
MR3
RW RW
TCK1
0 0 : f1 or f2 (5) 0 1 : f8 1 0 : f32 1 1 : fC32
RW
NOTES : 1. TA0OUT pin is N-channel open drain output. 2. Effective w hen the TAiTGH and TAiTGL bits in the ONSF or TRGSR register are "00b" (TAiIN pin input). 3. The port direction bit for the TAiIN pin is set to "0" (= input mode). 4. Set this bit to "1" (Pulse is output) to output PWM pulse. 5. Selected by PCLK0 bit in the PCLKR register.
Figure 14.12
TAiMR Register in PWM Mode
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14. Timers
1 / fi x (216 - 1)
Count source
Input signal to TAiIN pin
"H" "L"
Trigger is not generated by this signal 1 / fj x n
PWM pulse output from TAiOUT pin IR bit in TAiIC register
"H" "L" "1" "0"
fj : Frequency of count source (f1, f2, f8, f32, fC32) i = 0 to 2
Set to "0" upon accepting an interrupt request or by writing in program
NOTES : 1. n = 0000h to FFFEh. 2. This timing diagram is for the case where the TAi register is "0003h", the TAiTGH and TAiTGL bits in the ONSF or TRGSR register = 00b (TAiIN pin input), the MR1 bit of TAiMR register = 1 (rising edge), and the MR2 bit in the TAiMR register = 1 (trigger selected by TAiTGH and TAiTGL bits).
Figure 14.13
Example of 16-bit Pulse Width Modulator Operation
1 / fj x (m + 1) x (28 - 1)
Count source (1)
Input signal to TAiIN pin
"H" "L"
1 / fj x (m + 1) Underflow signal of 8-bit prescaler (2)
"H" "L"
1 / fj x (m + 1) x n PWM pulse output from TAiOUT pin
"H" "L" "1" "0"
IR bit in TAiIC register
fj : Frequency of count source (f1, f2, f8, f32, fC32) i = 0 to 2
Set to "0" upon accepting an interrupt request or by writing in program
NOTES : 1. The 8-bit prescaler counts the count source. 2. The 8-bit pulse width modulator counts the output from the 8-bit prescaler underflow signal. 3. m = 00h to FFh; n = 00h to FEh. 4. This timing diagram is for the case where the TAi register is "0202h", the TAiTGH and TAiTGL bits of ONSF or TRGSR register = 00b (TAiIN pin input), the MR1 bit of TAiMR register = 0 (falling edge), and the MR2 bit of TAiMR register = 1 (trigger selected by TAiTGH and TAiTGL bits).
Figure 14.14
Example of 8-bit Pulse Width Modulator Operation
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M16C/30P Group
14. Timers
14.2
Timer B
Figure 14.15 shows a Timer B Block Diagram. Figures 14.16 and 14.17 show registers related to the Timer B. Timer B supports the following three modes. Use the TMOD1 and TMOD0 bits in the TBiMR register (i = 0 to 2) to select the desired mode. * Timer Mode: The timer counts an internal count source. * Event Counter Mode: The timer counts pulses from an external device or overflows or underflows of other timers. * Pulse Period/Pulse Width Measurement Mode: The timer measures pulse period or pulse width of an external signal.
High-order Bits of Data Bus
Select Clock Source f1 or f2 f8 f32 fC32
TBj Overflow (1, 2)
00 01 10 11 TCK1 1 0 TCK1 to TCK0 00: Timer 10: Pulse Period and Pulse Width Measurement
Low-order Bits of Data Bus
8 low-order bits TMOD1 to TMOD0 8 high-order bits
Reload Register
Counter 01: Event Counter TBiS
TBiIN
Polarity Switching and Edge Pulse
Counter Reset Circuit
i=0 to 2 NOTES: 1. Overflows or underflows. 2. j=i-1, however, j=2 when i=0 TCK1 to TCK0, TMOD1 to TMOD0 : Bits in TAiMR register TBiS : Bits in the TABSR and the TBSR register
TBi Timer B0 Timer B1 Timer B2
Address 0391h - 0390h 0393h - 0392h 0395h - 0394h
TBj Timer B2 Timer B0 Timer B1
Figure 14.15
Timer B Block Diagram
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14. Timers
Timer Bi Mode Register (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address 039Bh to 039Dh TB0MR to TB2MR Bit Name Bit Symbol Operation Mode Select Bit TMOD0
After Reset 00XX0000b Function
b1 b0
RW RW
TMOD1 MR0 MR1 --
0 0 : Timer mode 0 1 : Event counter mode 1 0 : Pulse period measurement mode, pulse w idth measurement mode 1 1 : Do not set to this value Function varies w ith each operation mode
RW RW RW RW(1)
MR2 --(2) MR3 TCK0 TCK1 NOTES : 1. Timer B0. 2. Timer B1, Timer B2. RO RW RW
Count Source Select Bit
Function varies w ith each operation mode
Timer Bi Register (i=0 to 2)(1)
(b15) b7 (b8) b0 b7 b0
Symbol TB0 TB1 TB2 Mode Timer Mode Event Counter Mode Pulse Period Measurement Mode, Pulse Width Measurement Mode
Address 0391h, 0390h 0393h, 0392h 0395h, 0394h Function Divide the count source by n + 1 w here n = set value Divide the count source by n + 1 w here n = set value (2) Measures a pulse period or w idth
After Reset Indeterminate Indeterminate Indeterminate Setting Range 0000h to FFFFh 0000h to FFFFh -- RW RW RW RO
NOTES : 1. The register must be accessed in 16-bit units. 2. The timer counts pulses from an external device or overflow s or underflow s of other timers.
Figure 14.16
TBiMR and TBi Registers
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14. Timers
Count Start Flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TABSR Bit Symbol TA0S TA1S TA2S -- (b4-b3) TB0S TB1S TB2S
Address After Reset 0380h 000XX000b Bit Name Function 0 : Stops counting Timer A0 Count Start Flag 1 : Starts counting Timer A1 Count Start Flag Timer A2 Count Start Flag Nothing is assigned. When w rite, set to "0". When read, their contents are indeterminate. Timer B0 Count Start Flag Timer B1 Count Start Flag Timer B2 Count Start Flag 0 : Stops counting 1 : Starts counting
RW RW RW RW -- RW RW RW
Clock Prescaler Reset Flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol CPSRF Bit Symbol -- (b6-b0) CPSR
Address 0381h Bit Name Nothing is assigned. When w rite, set to "0". When read, their contents are indeterminate. Clock Prescaler Reset Flag
After Reset 0XXXXXXXb Function RW --
Setting this bit to "1" initializes the prescaler for the timekeeping clock. (When read, its content is "0".)
RW
Figure 14.17
TABSR and CPSRF Registers
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14. Timers
14.2.1
Timer Mode
In timer mode, the timer counts a count source generated internally (see Table 14.6). Figure 14.18 shows TBiMR Register in Timer Mode. Table 14.6 Specifications in Timer Mode
Item Count Source Count Operation
Divide Ratio Count Start Condition Count Stop Condition Interrupt Request Generation Timing TBiIN Pin Function Read from Timer Write to Timer
Specification f1, f2, f8, f32, fC32 * Down-count * When the timer underflows, it reloads the reload register contents and continues counting 1/(n+1) n: set value of TBi register (i= 0 to 2) 0000h to FFFFh Set TBiS bit(1) to "1" (= start counting) Set TBiS bit to "0" (= stop counting) Timer underflow I/O port Count value can be read by reading TBi register * When not counting and until the 1st count source is input after counting start Value written to TBi register is written to both reload register and counter * When counting (after 1st count source input) Value written to TBi register is written to only reload register (Transferred to counter when reloaded next)
NOTES: 1. The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register.
Timer Bi Mode Register (i= 0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol Address 039Bh to 039Dh TB0MR to TB2MR Bit Name Bit Symbol Operation Mode Select Bit TMOD0 TMOD1 MR0 Has no effect in timer mode Can be set to "0" or "1" MR1 TB0MR register Set to "0" in timer mode MR2
After Reset 00XX0000b Function
b1 b0
0 0 : Timer mode
RW RW RW RW RW RW
TB1MR, TB2MR registers Nothing is assigned. When w rite, set to "0". When read, its content is indeterminate When w rite in timer mode, set to "0". When read in timer mode, its content is indeterminate. Count Source Select Bit
b7 b6
--
MR3 TCK0
RO RW
TCK1 NOTES : 1. Selected by PCLK0 bit in the PCLKR register.
0 0 : f1 or f2 (1) 0 1 : f8 1 0 : f32 1 1 : fC32
RW
Figure 14.18
TBiMR Register in Timer Mode
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14. Timers
14.2.2
Event Counter Mode
In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers (see Table 14.7). Figure 14.19 shows TBiMR Register in Event Counter Mode. Table 14.7 Specifications in Event Counter Mode
Item Count Source
Count Operation
Specification * External signals input to TBiIN pin (i=0 to 2) (effective edge can be selected in program) * Timer Bj overflow or underflow (j=i-1, however, j=2 if i=0) * Down-count * When the timer underflows, it reloads the reload register contents and continues counting 1/(n+1) n: set value of TBi register Set TBiS bit(1) to "1" (= start counting) Set TBiS bit to "0" (= stop counting) Timer underflow Count source input Count value can be read by reading TBi register * When not counting and until the 1st count source is input after counting start Value written to TBi register is written to both reload register and counter * When counting (after 1st count source input) Value written to TBi register is written to only reload register (Transferred to counter when reloaded next) 0000h to FFFFh
Divide Ratio Count Start Condition Count Stop Condition Interrupt Request Generation Timing TBiIN Pin Function Read from Timer Write to Timer
NOTES: 1. The TB0S to TB2S bits are assigned to the TABSR register bit 5 to bit 7.
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14. Timers
Timer Bi Mode Register (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
01
Address Symbol 039Bh to 039Dh TB0MR to TB2MR Bit Name Bit Symbol TMOD0 Operation Mode Select Bit TMOD1 Count Polarity Select Bit (1) MR0
After Reset 00XX0000b Function
b1 b0
0 1 : Event counter mode
b3 b2
RW RW RW RW
MR1 TB0MR register Set to "0" in event counter mode MR2
0 0 : Counts falling edges of external signal 0 1 : Counts rising edges of external signal 1 0 : Counts falling and rising edges external signal 1 1 : Do not set to this value
RW
RW
TB1MR, TB2MR registers Nothing is assigned. When w rite, set to "0". When read, its content is indeterminate. When w rite in event counter mode, set to "0". When read in event counter mode, its content is indeterminate. Has no effect in event counter mode. Can be set to "0" or "1". Event Clock Select 0 : Input from TBiIN pin (2) 1 : TBj overflow or underflow (j = i - 1, how ever, j = 2 if i = 0)
--
MR3 TCK0
RO RW
TCK1
RW
NOTES : 1. Effective w hen the TCK1 bit = 0 (input from TBiIN pin). If the TCK1 bit = 1 (TBj overflow or underflow ), these bits can be set to "0" or "1". 2. The port direction bit for the TBiIN pin must be set to "0" (= input mode).
Figure 14.19
TBiMR Register in Event Counter Mode
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M16C/30P Group
14. Timers
14.2.3
Pulse Period and Pulse Width Measurement Mode
In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an external signal (see Table 14.8). Figure 14.20 shows TBiMR Register in Pulse Period and Pulse Width Measurement Mode. Figure 14.21 shows the Operation Timing when Measuring a Pulse Period. Figure 14.22 shows the Operation Timing when Measuring a Pulse Width. Table 14.8 Specifications in Pulse Period and Pulse Width Measurement Mode
Item Count Source Count Operation
Count Start Condition Count Stop Condition Interrupt Request Generation Timing
Specification f1, f2, f8, f32, fC32 * Up-count * Counter value is transferred to reload register at an effective edge of measurement pulse. The counter value is set to "0000h" to continue counting. Set TBiS (i=0 to 2) bit (3) to "1" (= start counting) Set TBiS bit to "0" (= stop counting) * When an effective edge of measurement pulse is input (1) * Timer overflow. When an overflow occurs, MR3 bit in the TBiMR register is set to "1" (overflowed) simultaneously. MR3 bit is set to "0" (no overflow) by writing to TBiMR register at the next count timing or later after MR3 bit was set to "1". At this time, make sure TBiS bit is set to "1" (start counting). Measurement pulse input Contents of the reload register (measurement result) can be read by reading TBi register (2) Value written to TBi register is written to neither reload register nor counter
TBiIN Pin Function Read from Timer Write to Timer
NOTES: 1. Interrupt request is not generated when the first effective edge is input after the timer started counting. 2. Value read from TBi register is indeterminate until the second valid edge is input after the timer starts counting. 3. The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register.
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14. Timers
Timer Bi Mode Register (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
10
Symbol Address 039Bh to 039Dh TB0MR to TB2MR Bit Name Bit Symbol Operation Mode Select Bit TMOD0 TMOD1 Measurement Mode Select Bit MR0
After Reset 00XX0000b Function
b1 b0
RW RW RW
1 0 : Pulse period / pulse w idth measurement mode
b3 b2
MR1
0 0 : Pulse period measurement (Measurement betw een a falling edge and the next falling edge of measured pulse) 0 1 : Pulse period measurement (Measurement betw een a rising edge and the next rising edge of measured pulse) 1 0 : Pulse w idth measurement (Measurement betw een a falling edge and the next rising edge of measured pulse and betw een a rising edge and the next falling edge) 1 1 : Do not set to this value
RW
RW
TB0MR register Set to "0" in pulse period and pulse w idth measurement mode MR2 TB1MR, TB2MR registers Nothing is assigned. When w rite, set to "0". When read, its content turns out to be indeterminate. Timer Bi Overflow Flag (1) Count Source Select Bit 0 : Timer did not overflow 1 : Timer has overflow ed
b7 b6
RW
--
MR3 TCK0
RO RW
TCK1
0 0 : f1 or f2 (2) 0 1 : f8 1 0 : f32 1 1 : fC32
RW
NOTES : 1. This flag is indeterminate after reset. When the TBiS bit = 1 (start counting), the MR3 bit is cleared to "0" (no overflow ) by w riting to the TBiMR register at the next count timing or later after the MR3 bit w as set to "1" (overflow ed). The MR3 bit cannot be set to "1" in a program. The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register. 2. Selected by PCLK0 bit in the PCLKR register.
Figure 14.20
TBiMR Register in Pulse Period and Pulse Width Measurement Mode
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14. Timers
Count source
Measurement pulse
"H" "L" Transfer (indeterminate value) Transfer (measured value)
Reload register transfer timing
counter
(NOTE 1) (NOTE 1) (NOTE 2)
Timing at which counter reaches "0000h" TBiS bit
"1" "0"
IR bit in TBiIC register
"1" "0"
MR3 bit in TBiMR register i = 0 to 2
"1" "0"
Set to "0" upon accepting an interrupt request or by writing in program
The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register. NOTES : 1. Counter is initialized at completion of measurement. 2. Timer has overflowed. 3. This timing diagram is for the case where the MR1 to MR0 bits in the TBiMR register are "00b" (measure the interval from falling edge to falling edge of the measurement pulse).
Figure 14.21
Operation Timing when Measuring a Pulse Period
Count source
Measurement pulse
"H" "L"
Transfer (indeterminate value) Transfer (measured value) Transfer (measured value) Transfer (measured value)
Reload register transfer timing
counter
(NOTE 1)
(NOTE 1)
(NOTE 1)
(NOTE 1)
(NOTE 2)
Timing at which counter reaches "0000h"
"1" "0"
TBiS bit
IR bit in TBiIC register
"1" "0" "1" "0"
MR3 bit in TBiMR register
Set to "0" upon accepting an interrupt request or by writing in program
The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register. i = 0 to 2 NOTES : 1. Counter is initialized at completion of measurement. 2. Timer has overflowed. 3. This timing diagram is for the case where the MR1 to MR0 bits in the TBiMR register are "10b" (measure the interval from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge of the measurement pulse).
Figure 14.22
Operation Timing when Measuring a Pulse Width
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M16C/30P Group
15. Serial Interface
15. Serial Interface
Serial interface is configured with 3 channels: UART0 to UART2.
15.1
UARTi (i=0 to 2)
UARTi each have an exclusive timer to generate a transfer clock, so they operate independently of each other. Figures 15.1 to 15.3 shows the block diagram of UART0 to UART2. Figure 15.4 shows the UARTi Transmit/ Receive Unit. UARTi has the following modes: * Clock synchronous serial I/O mode * Clock asynchronous serial I/O mode (UART mode). * Special mode 1 (I2C mode) * Special mode 2 * Special mode 3 (Bus collision detection function, IE mode) : UART2 * Special mode 4 (SIM mode) : UART2 Figures 15.5 to 15.11 show the UARTi-related registers. Refer to tables listing each mode for register setting.
PCLK1 1/2 f2SIO f1SIO 1/8 1/4 0 1 f1SIO or f2SIO f8SIO f32SIO TXD polarity reversing circuit Reception control circuit Receive clock Transmit/ receive unit
Main clock
(UART0)
RXD0
RXD polarity reversing circuit 1/16 UART reception SMD2 to SMD0 010, 100, 101, 110 Clock synchronous type 001 UART transmission 010, 100, 101, 110 Transmission control circuit
TXD0
Clock source selection
f1SIO or f2SIO CLK1 or CLK0 CKDIR 00 Internal 01 0 f8SIO 10 f32SIO 1 Extenal U0BRG register
1 / (n0+1)
1/16
Transmit clock
Clock synchronous type 001 Clock synchronous type (when internal clock is selected) 0 1/2 1 Clock synchronous type CKDIR (when external clock is selected)
CLK0
CKPOL CLK polarity reversing circuit CTS/RTS selected
Clock synchronous type (when internal clock is selected)
CTS/RTS disabled
CTS0 / RTS0
RTS0
0 1 RCSP 0 1 VSS CRD n0: Values set to the U0BRG register PCLK1: Bit in the PCLKR register SMD2 to SMD0, CKDIR: Bits in U0MR register CLK1 to CLK0, CKPOL, CRD, CRS: Bits in U0C0 register RCSP: Bits in UCON register CTS/RTS disabled
1 CRS 0 CTS0 from UART1
CTS0
Figure 15.1
UART0 Block Diagram
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15. Serial Interface
PCLK1 1/2 f2SIO f1SIO 1/8 0 1 f1SIO or f2SIO f8SIO 1/4 RXD polarity reversing circuit 1/16 f32SIO TXD polarity reversing circuit Receive clock Transmit/ receive unit
Main clock
(UART1)
RXD1
TXD1
Clock source selection
f1SIO or f2SIO CLK1 or CLK0 CKDIR 00 Internal 01 0 f8SIO 10 f32SIO 1 Extenal U1BRG register
UART reception SMD2 to SMD0 010, 100, 101, 110 Reception Clock synchronous control circuit type 001 UART transmission 010, 100, 101, 110 Clock synchronous type 001 Clock synchronous type (when internal clock is selected) 0 1 CKDIR
1 / (n1+1)
1/16
Transmission control circuit
Transmit clock
1/2 Clock synchronous type (when external clock is selected) CKPOL CLK polarity reversing circuit
CLK1
0
CLKMD0
Clock synchronous type (when internal clock is selected)
1
CTS1 / RTS1/ CTS0 / CLKS1
Clock output pin select
1
CTS/RTS selected CRS 1 0
CTS/RTS disabled
RTS1
CTS/RTS disabled
CLKMD1
0 0 1
0 1
CTS1
CTS0 from UART0
VSS n1: Values set to the U1BRG register PCLK1: Bit in the PCLKR register SMD2 to SMD0, CKDIR: Bits in U1MR register CLK1 to CLK0, CKPOL, CRD, CRS: Bits in U1C0 register CLKMD0, CLKMD1, RCSP: Bits in UCON register
CRD
RCSP
Figure 15.2
UART1 Block Diagram
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15. Serial Interface
1/2
f2SIO f1SIO
0 1
PCLK1 f1SIO or f2SIO f8SIO 1/4 f32SIO TXD polarity reversing circuit (1) Receive clock Transmit/ receive unit
Main clock
1/8
(UART2)
RXD2
RXD polarity reversing circuit 1/16 UART reception SMD2 to SMD0 010, 100, 101, 110 Reception Clock synchronous control circuit type 001
TXD2
Clock source selection
f1SIO or f2SIO CLK1 to CLK0 CKDIR 00 Internal 01 0 f8SIO 10 f32SIO 1 Extenal
U2BRG register
1 / (n2+1)
1/16
1/2
UART transmission Transmission 010, 100, 101, 110 control circuit Clock synchronous type 001 Clock synchronous type (when internal clock is selected) 0 1
Transmit clock
CLK2
CKPOL CLK polarity reversing circuit
Clock synchronous type (when internal clock is selected)
Clock synchronous type (when external clock is selected)
CKDIR
CTS/RTS disabled CTS/RTS selected
CTS2 / RTS2
RTS2
0 1 VSS CRD CTS/RTS disabled
1 CRS 0
CTS2
n2: Values set to the U2BRG register PCLK1: Bit in the PCLKR register SMD2 to SMD0, CKDIR: Bits in U2MR register CLK1 to CLK0, CKPOL, CRD, CRS: Bits in U2C0 register CLKMD0, CLKMD1, RCSP: Bits in UCON register NOTES : 1. UART2 is the N-channel open-drain output. Cannot be set to the CMOS output.
Figure 15.3
UART2 Block Diagram
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15. Serial Interface
IOPOL
0 No reverse
RXDi
RXD data reverse circuit
1 Reverse
Clock synchronous type
STPS 1SP 0 SP 1 2SP SP
PAR
PRYE
PAR disabled
Clock synchronous type
UART (7 bits) UART (8 bits)
UART(7 bits)
0
0
0
UARTi receive register
0 1
UART
1
PAR enabled
1
UART (9 bits)
SMD2 to SMD0
Clock synchronous type UART (8 bits) UART (9 bits)
1
0
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
UiRB register
Logic reverse circuit + MSB/LSB conversion circuit
Data bus high-order bits Data bus low-order bits
Logic reverse circuit + MSB/LSB conversion circuit
D8
D7
UART (8 bits) UART (9 bits)
D6
D5
D4
D3
D2
D1
D0
UiTB register
STPS 2SP 1 SP SP 0 1SP
PAR
PRYE
PAR enabled
SMD2 to SMD0
UART
UART (9 bits)
Clock synchronous type
1 0
1
1
1
0
PAR disabled
Clock synchronous type
0
UART (7 bits) UART (8 bits) Clock synchronous type
0 UART(7 bits)
Error signal output disable 0
UARTi transmit register
IOPOL
0
No reverse
i=0 to 2 SP: Stop bit PAR: Parity bit SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR: Bits in UiMR register UiERE: Bit in UiC1 register
UiERE 1
Error signal output circuit
1
TXD data reverse circuit
Reverse
TXDi
Error signal output enable
Figure 15.4
UARTi Transmit/Receive Unit
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UARTi Transmit Buffer Register (i=0 to 2)(1)
(b15) b7 (b8) b0 b7 b0
Symbol U0TB U1TB U2TB
Address 03A3h to 03A2h 03ABh to 03AAh 037Bh to 037Ah Function
After Reset Indeterminate Indeterminate Indeterminate RW WO --
Transmit data Nothing is assigned. When w rite, set to "0". When read, their contents are indeterminate. NOTES : 1. Use MOV instruction to w rite to this register.
UARTi Receive Buffer Register (i=0 to 2)
(b15) b7 (b8) b0 b7 b0
Symbol U0RB U1RB U2RB Bit Symbol -- (b7-b0) -- (b8) -- (b10-b9) ABT OER FER PER SUM Bit Name -- --
Address 03A7h to 03A6h 03AFh to 03AEh 037Fh to 037Eh Function Receive data (D7 to D0) Receive data (D8)
After Reset Indeterminate Indeterminate Indeterminate RW RO RO -- RW RO RO RO RO
Nothing is assigned. When w rite, set to "0". When read, their contents are "0". Arbitration Lost Detecting Flag (2) Overrun Error Flag (1) Framing Error Flag (1, 3) Parity Error Flag (1, 3) Error Sum Flag (1,3) 0 : Not detected 1 : Detected 0 : No overrun error 1 : Overrun error found 0 : No framing error 1 : Framing error found 0 : No parity error 1 : Parity error found 0 : No error 1 : Error found
NOTES : 1. When the SMD2 to SMD0 bits in the UiMR register = 000b (serial interface disabled) or the RE bit in the UiC1 register = 0 (reception disabled), all of the SUM, PER, FER and OER bits are set to "0" (no error). The SUM bit is set to "0" (no error) w hen all of the PER, FER and OER bits = 0 (no error). Also, the PER and FER bits are set to "0" by reading the low er byte of the UiRB register. 2. The ABT bit is set to "0" by w riting "0" in a program. (Writing "1" has no effect) 3. These error flags are disabled w hen the SMD2 to SMD0 bits are set to "001b" (clock synchronous serial I/O mode) or to "010b" (I2C mode). When read, the contents are indeterminate.
Figure 15.5
UiTB and UiRB Registers
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UARTi Bit Rate Generation Register (i=0 to 2) (1, 2, 3)
b7 b0
Symbol U0BRG U1BRG U2BRG Function
Address 03A1h 03A9h 0379h
After Reset Indeterminate Indeterminate Indeterminate Setting Range 00h to FFh RW WO
Assuming that set value = n, UiBRG divides the count source by n + 1 NOTES : 1. Write to this register w hile serial interface is neither transmitting nor receiving. 2. Use MOV instruction to w rite to this register. 3. Write to this register after setting the CLK1 to CLK0 bits in the UiC0 register.
UARTi Transmit/Receive Mode Register (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After Reset 03A0h, 03A8h, 0378h 00h U0MR to U2MR Bit Symbol Bit Name Function Serial I/O Mode Select Bit (2) b2 b1 b0 0 0 0 : Serial interface disabled SMD0 0 0 1 : Clock synchronous serial I/O mode 0 1 0 : I2C mode (3) 1 0 0 : UART mode transfer data 7 bits long SMD1 1 0 1 : UART mode transfer data 8 bits long 1 1 0 : UART mode transfer data 9 bits long SMD2 Do not set except above CKDIR STPS Internal/External Clock Select Bit Stop Bit Length Select Bit Odd/Even Parity Select Bit PRY Parity Enable Bit 0 : Internal clock 1 : External clock (1) 0 : 1 stop bit 1 : 2 stop bits Effective w hen PRYE = 1 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled
RW RW
RW
RW RW RW
RW
PRYE IOPOL
RW RW
TXD, RXD I/O Polarity Reverse 0 : No reverse Bit 1 : Reverse
NOTES : 1. Set the corresponding port direction bit for each CLKi pin to "0" (input mode). 2. To receive data, set the corresponding port direction bit for each RXDi pin to "0" (input mode). 3. Set the corresponding port direction bit for SCL and SDA pins to "0" (input mode).
Figure 15.6
UiBRG and UiMR Registers
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UARTi Transmit/Receive Control Register 0 (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
After Reset Address Symbol 00001000b 03A4h, 03ACh, 037Ch U0C0 to U2C0 Function Bit Name Bit Symbol BRG Count Source Select b1 b0 CLK0 0 0 : f1SIO or f2SIO is selected(6) Bit (5) 0 1 : f8SIO is selected 1 0 : f32SIO is selected CLK1 1 1 : Do not set to this value
_____ _____
RW RW
RW
CRS
CTS/RTS Function Select Bit (4)
Effective w hen CRD = 0 _____ 0 : CTS function is selected (1) _____ 1 : RTS function is selected 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed)
_____ ____
RW
TXEPT
Transmit Register Empty Flag
RO
_____ _____
CTS/RTS Disable Bit CRD
0 : CTS/RTS function enabled ____ ____ 1 : CTS/RTS function disabled (P6_0, P6_4 and P7_3 can be used as I/O ports) 0 : TXDi/SDAi and SCLi pins are CMOS output 1 : TXDi/SDAi and SCLi pins are N-channel open-drain output 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge 0 : LSB first 1 : MSB first
RW
Data Output Select Bit (2) NCH
RW
CLK Polarity Select Bit CKPOL
RW
UFORM
Transfer Format Select Bit (3)
RW
NOTES : _____ 1. Set the corresponding port direction bit for each CTSi pin to "0" (input mode). 2. TXD2/SDA2 and SCL2 are N-channel open-drain output. Cannot be set to the CMOS output. No NCH bit in U2C0 register is assigned. When w rite, set to "0". 3. The UFORM bit is enabled w hen the SMD2 to SMD0 bits in the UiMR register are set to "001b" (clock synchronous serial I/O mode), or "101b" (UART mode, 8-bit transfer data). Set this bit to "1" w hen the SMD2 to SMD0 bits are set to "010b" (I2C mode), and to "0" w hen the SMD2 to SMD0 bits are set to "100b" (UART mode, 7-bit transfer data) or "110b" (UART mode, 9-bit transfer data). 4. CTS1/RTS1 can be used w hen the CLKMD1 bit in the UCON register = 0 (only CLK1 output) and the RCSP
______ ______ ______ ______
bit in the UCON register = 0 (CTS0/RTS0 not separated). 5. When changing the CLK1 to CLK0 bits, set the UiBRG register. 6. Selected by PCLK1 bit in the PCLKR register.
Figure 15.7
UiC0 to UiC2 Register
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UARTi Transmit/Receive Control Register 1 (i=0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address 03A5h, 03ADh U0C1, U1C1 Bit Name Bit Symbol Transmit Enable Bit TE TI RE RI -- (b5-b4) UiLCH UiERE Transmit Buffer Empty Flag Receive Enable Bit Receive Complete Flag
After Reset 00XX0010b Function 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in UiTB register 1 : No data present in UiTB register 0 : Reception disabled 1 : Reception enabled 0 : No data present in UiRB register 1 : Data present in UiRB register
RW RW RO RW RO -- RW RW
Nothing is assigned. When w rite, set to "0". When read, these contents are indeterminate. Data Logic Select Bit (1) Error Signal Output Enable Bit 0 : No reverse 1 : Reverse 0 : Output disabled 1 : Output enabled
NOTES : 1. The UiLCH bit is enabled w hen the SMD2 to SMD0 bits in the UiMR register are set to "001b" (clock synchronous serial I/O mode), "100b" (UART mode, 7-bit transfer data), or "101b" (UART mode, 8-bit transfer data). Set this bit to "0" w hen the SMD2 to SMD0 bits are set to "010b" (I2C mode) or "110b" (UART mode, 9-bit transfer data).
UART2 Transmit/Receive Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U2C1 Bit Symbol TE TI RE RI U2IRS U2RRM U2LCH U2ERE
Address 037Dh Bit Name Transmit Enable bit Transmit Buffer Empty Flag Receive Enable Bit Receive Complete Flag UART2 Transmit Interrupt Factor Select Bit
After Reset 00000010b Function 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in U2TB register 1 : No data present in U2TB register 0 : Reception disabled 1 : Reception enabled 0 : No data present in U2RB register 1 : Data present in U2RB register 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1)
RW RW RO RW RO RW RW RW RW
UART2 Continuous Receive Mode 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled Enable Bit Data Logic Select Bit (1) Error Signal Output Enable Bit 0 : No reverse 1 : Reverse 0 : Output disabled 1 : Output enabled
NOTES : 1. The U2LCH bit is enabled w hen the SMD2 to SMD0 bits in the U2MR register are set to "001b" (clock synchronous serial I/O mode), "100b" (UART mode, 7-bit transfer data), or "101b" (UART mode, 8-bit transfer data). Set this bit to "0" w hen the SMD2 to SMD0 bits are set to "010b" (I2C mode) or "110b" (UART mode, 9-bit transfer data).
Figure 15.8
U0C1 to U2C1 Registers
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UART Transmit/Receive Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After Reset 03B0h X0000000b UCON Bit Symbol Bit Name Function UART0 Transmit Interrupt Factor 0 : Transmit buffer empty (Tl = 1) U0IRS Select Bit 1 : Transmission completed (TXEPT = 1) U1IRS U0RRM U1RRM UART1 Transmit Interrupt Factor 0 : Transmit buffer empty (Tl = 1) Select Bit 1 : Transmission completed (TXEPT = 1) UART0 Continuous Receive Mode Enable Bit UART1 Continuous Receive Mode Enable Bit UART1 CLK/CLKS Select Bit 0 CLKMD0 0 : Continuous receive mode disabled 1 : Continuous receive mode enable 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled Effective w hen CLKMD1 = 1 0 : Clock output from CLK1 1 : Clock output from CLKS1
RW RW RW RW RW
RW
CLKMD1
UART1 CLK/CLKS Select Bit 1 (1) 0 : CLK output is only CLK1 1 : Transfer clock output from multiple pins function selected
_____ _____
RW
RCSP
Separate UART0 CTS/RTS Bit
_____ _____
0 : CTS/RTS shared pin _____ _____ 1 : CTS/RTS separated (CTS0 supplied from the P6_4 pin)
RW
-- (b7)
Nothing is assigned. When w rite, set to "0". When read, its content is indeterminate.
--
NOTES : 1. When using multiple transfer clock output pins, make sure the follow ing conditions are met: CKDIR bit in the U1MR register = 0 (internal clock)
UARTi Special Mode Register (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
0
After Reset Symbol Address X0000000b 036Fh, 0373h, 0377h U0SMR to U2SMR Bit Name Function Bit Symbol I2C Mode Select Bit 0 : Other than I2C mode IICM 1 : I2C mode ABC BBS -- (b3) ABSCS ACSE SSS -- (b7) Arbitration Lost Detecting Flag Control Bit Bus Busy Flag Reserved Bit Bus Collision Detect Sampling Clock Select Bit Auto Clear Function Select Bit of Transmit Enable Bit Transmit Start Condition Select Bit 0 : Update per bit 1 : Update per byte 0 : STOP condition detected 1 : START condition detected (busy) Set to "0" 0 : Rising edge of transfer clock 1 : Underflow signal of timer Aj (2) 0 : No auto clear function 1 : Auto clear at occurrence of bus collision 0 : Not synchronized to RXDi 1 : Synchronized to RXDi (3)
RW RW RW RW(1) RW RW RW RW --
Nothing is assigned. When w rite, set to "0". When read, its content is indeterminate.
NOTES : 1. The BBS bit is set to "0" by w riting "0" in a program (Writing "1" has no effect). 2. Underflow signal of timer A0 in UART2. 3. When a transfer begins, the SSS bit is set to "0" (Not synchronized to RXDi).
Figure 15.9
UCON and UiSMR Registers
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UARTi Special Mode Register 2 (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After Reset 036Eh, 0372h, 0376h X0000000b U0SMR2 to U2SMR2 Bit Name Function Bit Symbol I2C Mode Select Bit 2 See Table 15.13 I2C Mode Functions IICM2 CSC SWC ALS STAC SWC2 SDHI -- (b7) Clock-Synchronous Bit SCL Wait Output Bit SDA Output Stop Bit UARTi Initialization Bit SCL Wait Output Bit 2 SDA Output Disable Bit 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0: Transfer clock 1: "L" output 0: Enabled 1: Disabled (high-impedance)
RW RW RW RW RW RW RW RW --
Nothing is assigned. When w rite, set to "0". When read, its content is indeterminate.
UARTi special mode register 3 (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
After Reset Symbol Address 000X0X0Xb 036Dh, 0371h, 0375h U0SMR3 to U2SMR3 Bit Name Function Bit Symbol -- Nothing is assigned. (b0) When w rite, set "0". When read, its content is indeterminate. CKPH -- (b2) NODC -- (b4) DL0 Clock Phase Set Bit 0 : Without clock delay 1 : With clock delay
RW -- RW -- RW --
Nothing is assigned. When w rite, set "0". When read, its content is indeterminate. Clock Output Select Bit 0 : CLKi is CMOS output 1 : CLKi is N-channel open drain output
Nothing is assigned. When w rite, set to "0". When read, its content is indeterminate. SDAi Digital Delay Setup Bit (1, 2)
b7 b6 b5
DL1
DL2
0 0 0 : Without delay 0 0 1 : 1 to 2 cycle(s) of UiBRG count source 0 1 0 : 2 to 3 cycles of UiBRG count source 0 1 1 : 3 to 4 cycles of UiBRG count source 1 0 0 : 4 to 5 cycles of UiBRG count source 1 0 1 : 5 to 6 cycles of UiBRG count source 1 1 0 : 6 to 7 cycles of UiBRG count source 1 1 1 : 7 to 8 cycles of UiBRG count source
RW
RW
RW
NOTES : 1. The DL2 to DL0 bits are used to generate a delay in SDAi output by digital means during I2C mode. In other than I2C mode, set these bits to "000b" (no delay). 2. The amount of delay varies w ith the load on SCLi and SDAi pins. Also, w hen using an external clock, the amount of delay increases by about 100 ns.
Figure 15.10
UiSMR2 and UiSMR3 Registers
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UARTi Special Mode Register 4 (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address 036Ch, 0370h, 0374h U0SMR4 to U2SMR4 Bit Name Bit Symbol Start Condition Generate Bit (1) 0 : Clear STAREQ 1 : Start RSTAREQ STPREQ Restart Condition Generate Bit (1) Stop Condition Generate Bit (1) SCL,SDA Output Select Bit STSPSEL 0 : Clear 1 : Start 0 : Clear 1 : Start
After Reset 00h Function
RW RW RW RW
0 : Start and stop conditions not output 1 : Start and stop conditions output
RW
ACKD ACKC SCLHI SWC9
ACK Data Bit ACK Data Output Enable Bit SCL Output Stop Enable Bit SCL Wait Bit 3
0 : ACK 1 : NACK 0 : Serial interface data output 1 : ACK data output 0 : Disabled 1 : Enabled 0 : SCL "L" hold disabled 1 : SCL "L" hold enabled
RW RW RW RW
NOTES : 1. Set to "0" w hen each condition is generated.
Figure 15.11
UiSMR4 Register
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15.1.1
Clock Synchronous Serial I/O Mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 15.1 lists the Clock Synchronous Serial I/O Mode Specifications. Table 15.2 lists the Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode. Table 15.1 Clock Synchronous Serial I/O Mode Specifications
Specification Transfer data length: 8 bits * CKDIR bit in the UiMR(i=0 to 2) register = 0 (internal clock) : fj/ (2(n+1)) fj = f1SIO, f2SIO, f8SIO, f32SIO n: Setting value of UiBRG register 00h to FFh * CKDIR bit = 1 (external clock) : Input from CLKi pin Selectable from CTS function, RTS function or CTS/RTS function disable Before transmission can start, the following requirements must be met (1) * The TE bit in the UiC1 register = 1 (transmission enabled) * The TI bit in the UiC1 register = 0 (data present in UiTB register) * If CTS function is selected, input on the CTSi pin = L Before reception can start, the following requirements must be met (1) * The RE bit in the UiC1 register = 1 (reception enabled) * The TE bit in the UiC1 register = 1 (transmission enabled) * The TI bit in the UiC1 register = 0 (data present in the UiTB register) For transmission, one of the following conditions can be selected * The UiIRS bit (3) = 0 (transmit buffer empty): when transferring data from the UiTB register to the UARTi transmit register (at start of transmission) * The UiIRS bit =1 (transfer completed): when the serial interface finished sending data from the UARTi transmit register For reception * When transferring data from the UARTi receive register to the UiRB register (at completion of reception) Overrun error (2) This error occurs if the serial interface started receiving the next data before reading the UiRB register and received the 7th bit of the next data * CLK polarity selection Transfer data input/output can be chosen to occur synchronously with the rising or the falling edge of the transfer clock * LSB first, MSB first selection Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can be selected * Continuous receive mode selection Reception is enabled immediately by reading the UiRB register * Switching serial data logic This function reverses the logic value of the transmit/receive data * Transfer clock output from multiple pins selection (UART1) The output pin can be selected in a program from two UART1 transfer clock pins that have been set * Separate CTS/RTS pins (UART0) CTS0 and RTS0 are input/output from separate pins
Item Transfer Data Format Transfer Clock
Transmission, Reception Control Transmission Start Condition
Reception Start Condition
Interrupt Request Generation Timing
Error Detection
Select Function
NOTES: 1. When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0 register = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the external clock is in the high state; if the CKPOL bit in the UiC0 register = 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state. 2. If an overrun error occurs, bits 8 to 0 in the UiRB register are undefined. The IR bit in the SiRIC register does not change to "1" (interrupt requested). 3. The U0IRS and U1IRS bits respectively are the bits 0 and 1 in the UCON register; the U2IRS bit is the bit 4 in the U2C1 register.
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Table 15.2
Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode
Register UiTB (3) UiRB (3) UiBRG UiMR (3)
UiC0
Bit 0 to 7 0 to 7 OER 0 to 7 SMD2 to SMD0 CKDIR IOPOL CLK1 to CLK0 CRS TXEPT CRD
Function Set transmission data Reception data can be read Overrun error flag Set a bit rate Set to "001b" Select the internal clock or external clock Set to "0" Select the count source for the UiBRG register Select CTS or RTS to use Transmit register empty flag
UiC1
UiSMR UiSMR2 UiSMR3
UiSMR4 UCON
Enable or disable the CTS or RTS function NCH Select TXDi pin output mode (2) CKPOL Select the transfer clock polarity UFORM Select the LSB first or MSB first TE Set this bit to "1" to enable transmission/reception TI Transmit buffer empty flag RE Set this bit to "1" to enable reception RI Reception complete flag Select the source of UART2 transmit interrupt U2IRS (1) U2RRM (1) Set this bit to "1" to use continuous receive mode UiLCH Set this bit to "1" to use inverted data logic UiERE Set to "0" 0 to 7 Set to "0" 0 to 7 Set to "0" 0 to 2 Set to "0" NODC Select clock output mode 4 to 7 Set to "0" 0 to 7 Set to "0" U0IRS, U1IRS Select the source of UART0/UART1 transmit interrupt U0RRM, U1RRM Set this bit to "1" to use continuous receive mode CLKMD0 Select the transfer clock output pin when CLKMD1 = 1 CLKMD1 Set this bit to "1" to output UART1 transfer clock from two pins RCSP Set this bit to "1" to accept as input the CTS0 signal of the UART0 from the P6_4 pin 7 Set to "0"
NOTES: 1. Set the bit 4 and bit 5 in the U0C1 and U1C1 register to "0". The U0IRS, U1IRS, U0RRM and U1RRM bits in the UCON register. 2. TXD2 pin is N channel open-drain output. Set the NCH bit in the U2C0 register to "0". 3. Not all register bits are described above. Set those bits to "0" when writing to the registers in clock synchronous serial I/O mode. i=0 to 2
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Table 15.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Table 15.3 shows pin functions for the case where the multiple transfer clock output pin select function is deselected. Table 15.4 lists the P6_4 Pin Functions during clock synchronous serial I/O mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TXDi pin outputs an "H" (If the Nchannel open-drain output is selected, this pin is in a high-impedance state). Table 15.3 Pin Functions (when not select multiple transfer clock output pin function)
Pin Name TXDi (i = 0 to 2) (P6_3, P6_7, P7_0) RXDi (P6_2, P6_6, P7_1) CLKi (P6_1, P6_5, P7_2)
Function Method of Selection Serial Data Output (Outputs dummy data when performing reception only)
Serial Data Input
Transfer Clock Output Transfer Clock Input CTS Input
PD6_2 bit and PD6_6 bit in the PD6 register = 0, PD7_1 bit in the PD7 register = 0 (Can be used as an input port when performing transmission only) CKDIR bit in the UiMR register = 0 CKDIR bit = 1 PD6_1 bit and PD6_5 bit in the PD6 register = 0, PD7_2 bit in the PD7 register = 0 CRD bit in the UiC0 register = 0 CRS bit in the UiC0 register = 0 PD6_0 and PD6_4 bit in the PD6 register = 0, PD7_3 bit in the PD7 register = 0 CRD bit = 0 CRS bit = 1 CRD bit = 1
CTSi/RTSi (P6_0, P6_4, P7_3)
RTS Output I/O Port
Table 15.4 P6_4 Pin Functions
Pin Function P6_4 CTS1 RTS1 CTS0 (1) CLKS1
U1C0 Register CRD CRS - 1 0 0 0 0
-
Bit Set Value UCON Register RCSP CLKMD1 CLKMD0 0 0 - 0 0 - 0 1
-
PD6 Register PD6_4 Input: 0, Output: 1 0
-
1 0
-
0 0 1
(2)
- -
0
-
1
- : "0" or "1" NOTES: 1. In addition to this, set the CRD bit in the U0C0 register to "0" (CTS0/RTS0 enabled) and the CRS bit in the U0C0 register to "1" (RTS0 selected). 2. When the CLKMD1 bit = 1 and the CLKMD0 bit = 0, the following logic levels are output: *High if the CLKPOL bit in the U1C0 register = 0 *Low if the CLKPOL bit = 1
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(1) Example of Transmit Timing (when internal clock is selected) Tc
Transfer clock
"1" "0" "1" "0" "H" Data is transferred from the UiTB register to the UARTi transmit register Data is set in the UiTB register
TE bit in UiC1 register TI bit in UiC1 register CTSi
"L"
TCLK
Pulse stops because an "H" signal is applied to CTSi
Pulse stops because the TE bit is set to "0"
CLKi
TXDi TXEPT bit in UiC0 register IR bit in SiTIC register i = 0 to 2
"1" "0" "1" "0"
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
Set to "0" by an interrupt request acknowledgement or by program The above timing diagram applies to the case where the register bits are set as follows: * CKDIR bit in UiMR register = 0 (internal clock) * CRD bit in UiC0 register = 0 (CTS/RTS enabled), CRS bit = 0 (CTS selected) * CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock) * UiIRS bit = 0 (an interrupt request occurs when the transmit buffer becomes empty): U0IRS bit is bit 0 in UCON register U1IRS bit is bit 1 in UCON register U2IRS bit is bit 4 in U2C1 register TC = TCLK = 2(n + 1) / fj fj: frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO) n: value set to UiBRG register
(2) Example of Receive Timing (when external clock is selected)
RE bit in UiC1 register TE bit in UiC1 register TI bit in UiC1 register
RTSi "L" "1" "0" "1" "0" "1" "0" "H"
Dummy data is set in the to UiTB register
Data is transferred from the UiTB register to the UARTi transmit register
An "L" signal is applied when the UiRB register is read
1 / fEXT
CLKi
Received data is taken in RXDi D0 D1 D2 D3 D4 D5 D6 D7 "1" receive register to the UiRB register "0" "1" "0" D0 D1 D2 D3 D4 D5 D6 Read by the UiRB register D7 D0 D1 D2 D3 D4 D5 D6
RI bit in UiC1 register IR bit in SiRIC register
Data is transferred from the UARTi
Set to "0" by an interrupt request acknowledgement or by program
OER flag in UiRB "1" register "0"
i=0 to 2 The above timing diagram applies to the case where the register bits are set Make sure the following conditions are met when input to as follows: the CLKi pin before receiving data is high: * CKDIR bit in UiMR register = 1 (external clock) * TE bit in UiC0 register = 1 (transmit enabled) * CRD bit in UiC0 register = 0 (CTS/RTS enabled), CRS bit = 1 (RTS selected) * RE bit in UiC0 register = 1 (receive enabled) * CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and receive * Write dummy data to the UiTB register data taken in at the rising edge of the transfer clock) fEXT: frequency of external clock
Figure 15.12
Transmit and Receive Operation
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15.1.1.1
Counter Measure for Communication Error Occurs
If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode, follow the procedures below. * Resetting the UiRB register (i=0 to 2) (1) Set the RE bit in the UiC1 register to "0" (reception disabled) (2) Set the SMD2 to SMD0 bits in the UiMR register to "000b" (Serial interface disabled) (3) Set the SMD2 to SMD0 bits in the UiMR register to "001b" (Clock synchronous serial I/O mode) (4) Set the RE bit in the UiC1 register to "1" (reception enabled)
* Resetting the UiTB register (i=0 to 2) (1) Set the SMD2 to SMD0 bits in the UiMR register "000b" (Serial interface disabled) (2) Set the SMD2 to SMD0 bits in the UiMR register "001b" (Clock synchronous serial I/O mode) (3) "1" is written to RE bit in the UiC1 register (transmission enabled), regardless of the TE bit in the UiCi register
15.1.1.2
CLK Polarity Select Function
Use the CKPOL bit in the UiC0 register (i = 0 to 2) to select the transfer clock polarity. Figure 15.13 shows the Transfer Clock Polarity.
(1) When the CKPOL bit in the UiC0 register = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock)
CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 (NOTE 2)
(2) When the CKPOL bit = 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock)
CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 (NOTE 3)
NOTES: 1. This applies to the case where the UFORM bit in the UiC0 register = 0 (LSB first) and the UiLCH bit in the UiC1 register = 0 (no reverse). 2. When not transferring, the CLKi pin outputs a high signal. 3. When not transferring, the CLKi pin outputs a low signal. i = 0 to 2
Figure 15.13 Transfer Clock Polarity
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15.1.1.3
LSB First/MSB First Select Function
Use the UFORM bit in the UiC0 register (i = 0 to 2) to select the transfer format. Figure 15.14 shows the Transfer Format.
(1) When the UFORM bit in the UiC0 register = 0 (LSB first)
CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7
(2) When the UFORM bit = 1 (MSB first)
CLKi TXDi RXDi D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0
NOTES: 1. This applies to the case where the CKPOL bit in the UiC0 register = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock) and the UiLCH bit in the UiC1 register = 0 (no reverse). i = 0 to 2
Figure 15.14 Transfer Format
15.1.1.4
Continuous Receive Mode
In continuous receive mode, receive operation becomes enable when the receive buffer register is read. It is not necessary to write dummy data into the transmit buffer register to enable receive operation in this mode. However, a dummy read of the receive buffer register is required when starting the operation mode. When the UiRRM bit (i = 0 to 2) = 1 (continuous receive mode), the TI bit in the UiC1 register is set to "0" (data present in the UiTB register) by reading the UiRB register. In this case, i.e., UiRRM bit = 1, do not write dummy data to the UiTB register in a program. The U0RRM and U1RRM bits are the bit 2 and bit 3 in the UCON register, respectively, and the U2RRM bit is the bit 5 in the U2C1 register.
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15.1.1.5
Serial Data Logic Switching Function
When the UiLCH bit in the UiC1 register (i = 0 to 2) = 1 (reverse), the data written to the UiTB register has its logic reversed before being transmitted. Similarly, the received data has its logic reversed when read from the UiRB register. Figure 15.15 shows Serial Data Logic Switching.
(1) When The UiLCH Bit in The UiC1 Register = 0 (No Reverse)
Transfer Clock TXDi (No Reverse)
"H" "L" "H" "L"
D0
D1
D2
D3
D4
D5
D6
D7
(2) When The UiLCH Bit = 1 (Reverse)
Transfer Clock TXDi (Reverse)
"H" "L" "H" "L"
D0
D1
D2
D3
D4
D5
D6
D7
NOTES : 1. This applies to the case where the CKPOL bit in the UiC0 register = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock) and the UFORM bit = 0 (LSB first). i = 0 to 2
Figure 15.15 Serial Data Logic Switching
15.1.1.6
Transfer Clock Output From Multiple Pins (UART1)
Use the CLKMD1 to CLKMD0 bits in the UCON register to select one of the two transfer clock output pins (see Figure 15.16). This function can be used when the selected transfer clock for UART1 is an internal clock.
Microcomputer
TXD1 (P6_7)
CLKS1 (P6_4) CLK1 (P6_5) IN CLK IN CLK
Transfer enabled when the CLKMD0 bit in the UCON register = 0
Transfer enabled when the CLKMD0 bit = 1
NOTES : 1. This applies to the case where the CKDIR bit in the U1MR register= 0 (internal clock) and the CLKMD1 bit in the UCON register = 1 (transfer clock output from multiple pins).
Figure 15.16 Transfer Clock Output from Multiple Pins
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15.1.1.7
CTS/RTS Function
When the CTS function is used transmit and receive operation start when "L" is applied to the CTSi/RTSi (i=0 to 2) pin. Transmit and receive operation begins when the CTSi/RTSi pin is held "L". If the "L" signal is switched to "H" during a transmit or receive operation, the operation stops before the next data. When the RTS function is used, the CTSi/RTSi pin outputs on "L" signal when the microcomputer is ready to receive. The output level becomes "H" on the first falling edge of the CLKi pin. * CRD bit in UiC0 register = 1 (disable CTS/RTS of UART0) CTSi/RTSi pin is programmable I/O function * CRD bit = 0, CRS bit = 0 (CTS function is selected) CTSi/RTSi pin is CTS function * CRD bit = 0, CRS bit = 1 (RTS function is selected) CTSi/RTSi pin is RTS function
15.1.1.8
CTS/RTS Separate Function (UART0)
This function separates CTS0/RTS0, outputs RTS0 from the P6_0 pin, and accepts as input the CTS0 from the P6_4 pin. To use this function, set the register bits as shown below. * CRD bit in U0C0 register = 0 (enable CTS/RTS of UART0) * CRS bit in U0C0 register = 1 (output RTS of UART0) * CRD bit in U1C0 register = 0 (enable CTS/RTS of UART1) * CRS bit in U1C0 register = 0 (input CTS of UART1) * RCSP bit in UCON register = 1 (inputs CTS0 from the P6_4 pin) * CLKMD1 bit in UCON register = 0 (CLKS1 not used) Note that when using the CTS/RTS separate function, CTS/RTS of UART1 separate function cannot be used.
Microcomputer
TXD0 (P6_3) RXD0 (P6_2) CLK0 (P6_1) IN OUT CLK CTS RTS
IC
RTS0 (P6_0) CTS0 (P6_4)
Figure 15.17
CTS/RTS Separate Function
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15.1.2
Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows transmitting and receiving data after setting the desired bit rate and transfer data format. Table 15.5 lists the UART Mode Specifications. Table 15.5 UART Mode Specifications
Specification * Character bit (transfer data): Selectable from 7, 8 or 9 bits * Start bit: 1 bit * Parity bit: Selectable from odd, even, or none * Stop bit: Selectable from 1 or 2 bits * CKDIR bit in the UiMR(i=0 to 2) register = 0 (internal clock) : fj/ (16(n+1)) fj = f1SIO, f2SIO, f8SIO, f32SIO n: Setting value of UiBRG register 00h to FFh * CKDIR bit = 1 (external clock) : fEXT/(16(n+1)) fEXT: Input from CLKi pin n :Setting value of UiBRG register 00h to FFh Selectable from CTS function, RTS function or CTS/RTS function disable Before transmission can start, the following requirements must be met * The TE bit in the UiC1 register= 1 (transmission enabled) * The TI bit in the UiC1 register = 0 (data present in UiTB register) * If CTS function is selected, input on the CTSi pin = L Before reception can start, the following requirements must be met * The RE bit in the UiC1 register = 1 (reception enabled) * Start bit detection For transmission, one of the following conditions can be selected * The UiIRS bit (2) = 0 (transmit buffer empty): when transferring data from the UiTB register to the UARTi transmit register (at start of transmission) * The UiIRS bit =1 (transfer completed): when the serial interface finished sending data from the UARTi transmit register For reception * When transferring data from the UARTi receive register to the UiRB register (at completion of reception) * Overrun error (1) This error occurs if the serial interface started receiving the next data before reading the UiRB register and received the bit one before the last stop bit of the next data * Framing error (3) This error occurs when the number of stop bits set is not detected * Parity error (3) This error occurs when if parity is enabled, the number of "1" in parity and character bits does not match the number of "1" set * Error sum flag This flag is set to "1" when any of the overrun, framing or parity errors occur * LSB first, MSB first selection Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can be selected * Serial data logic switch This function reverses the logic of the transmit/receive data. The start and stop bits are not reversed. * TXD, RXD I/O polarity switch This function reverses the polarities of the TXD pin output and RXD pin input. The logic levels of all I/O data is reversed. * Separate CTS/RTS pins (UART0) CTS0 and RTS0 are input/output from separate pins
Item Transfer Data Format
Transfer Clock
Transmission, Reception Control Transmission Start Condition
Reception Start Condition
Interrupt Request Generation Timing
Error Detection
Select Function
NOTES: 1. If an overrun error occurs, bits 8 to 0 in the UiRB register are undefined. The IR bit in the SiRIC register does not change to "1" (interrupt requested). 2. The U0IRS and U1IRS bits are bits 0 and 1 in the UCON register. The U2IRS bit is bit 4 in the U2C1 register. 3. The timing at which the framing error flag and the parity error flag are set is detected when data is transferred from the UARTi receive register to the UiRB register.
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Table 15.6
Register UiTB UiRB UiBRG UiMR
Registers to Be Used and Settings in UART Mode
Bit 0 to 8 0 to 8 OER,FER,PER,SUM 0 to 7 SMD2 to SMD0
(1)
Function Set transmission data Reception data can be read (1) Error flag Set a bit rate Set these bits to "100b" when transfer data is 7 bits long Set these bits to "101b" when transfer data is 8 bits long Set these bits to "110b" when transfer data is 9 bits long Select the internal clock or external clock Select the stop bit Select whether parity is included and whether odd or even Select the TXD/RXD input/output polarity Select the count source for the UiBRG register Select CTS or RTS to use Transmit register empty flag Enable or disable the CTS or RTS function Select TXDi pin output mode (3) Set to "0" LSB first or MSB first can be selected when transfer data is 8 bits long. Set this bit to "0" when transfer data is 7 or 9 bits long. Set this bit to "1" to enable transmission Transmit buffer empty flag Set this bit to "1" to enable reception Reception complete flag Select the source of UART2 transmit interrupt Set to "0" Set this bit to "1" to use inverted data logic Set to "0" Set to "0" Set to "0" Set to "0" Set to "0" Select the source of UART0/UART1 transmit interrupt Set to "0" Invalid because CLKMD1 = 0 Set to "0" Set this bit to "1" to accept as input CTS0 signal of UART0 from the P6_4 pin Set to "0"
UiC0
CKDIR STPS PRY, PRYE IOPOL CLK0, CLK1 CRS TXEPT CRD NCH CKPOL UFORM
UiC1
UiSMR UiSMR2 UiSMR3 UiSMR4 UCON
TE TI RE RI U2IRS (2) U2RRM (2) UiLCH UiERE 0 to 7 0 to 7 0 to 7 0 to 7 U0IRS, U1IRS U0RRM, U1RRM CLKMD0 CLKMD1 RCSP 7
NOTES: 1. The bits used for transmit/receive data are as follows: Bit 0 to bit 6 when transfer data is 7 bits long; bit 0 to bit 7 when transfer data is 8 bits long; bit 0 to bit 8 when transfer data is 9 bits long. 2. Set the bit 4 to bit 5 in the U0C1 and U1C1 registers to "0". The U0IRS, U1IRS, U0RRM and U1RRM bits are included in the UCON register. 3. TXD2 pin is N channel open-drain output. Set the NCH bit in the U2C0 register to "0". i=0 to 2
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Table 15.7 lists the functions of the input/output pins during UART mode. Table 15.8 lists the P6_4 Pin Functions. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TXDi pin outputs an "H" (If the N-channel open-drain output is selected, this pin is in a high-impedance state). Table 15.7 I/O Pin Functions
Pin Name TXDi (i = 0 to 2) (P6_3, P6_7, P7_0) RXDi (P6_2, P6_6, P7_1) CLKi (P6_1, P6_5, P7_2) CTSi/RTSi (P6_0, P6_4, P7_3)
Function Method of Selection Serial Data Output ("H" outputs when performing reception only)
Serial Data Input
Input/Output Port Transfer Clock Input CTS Input
RTS Output Input/Output Port
Table 15.8 P6_4 Pin Functions
PD6_2 bit and PD6_6 bit in the PD6 register = 0, PD7_1 bit in the PD7 register = 0 (Can be used as an input port when performing transmission only) CKDIR bit in the UiMR register = 0 CKDIR bit = 1 PD6_1 bit and PD6_5 bit in the PD6 register = 0, PD7_2 bit in the PD7 register = 0 CRD bit in the UiC0 register = 0 CRS bit in the UiC0 register = 0 PD6_0 bit and PD6_4 bit in the PD6 register = 0, PD7_3 bit in the PD7 register = 0 CRD bit = 0 CRS bit = 1 CRD bit = 1
Pin Function P6_4 CTS1 RTS1 CTS0 (1)
U1C0 Register CRD CRS - 1 0 0 0 0 1 0
Bit Set Value UCON Register RCSP CLKMD1 0 0 0 0 0 1 0 0
PD6 Register PD6_4 Input: 0, Output: 1 0
-
0
- : "0" or "1" NOTES: 1. In addition to this, set the CRD bit in the U0C0 register to "0" (CTS0/RTS0 enabled) and the CRS bit in the U0C0 register to "1" (RTS0 selected).
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(1) 8-bit Data Transmit Timing (with a parity and 1 stop bit) Tc
Transfer Clock TE bit in UiC1 register TI bit in UiC1 register
"1" "0" "1" "0" "H"
The transfer clock stops momentarily, because an "H" single is applied to the CTS pin, when the stop bit is verified. The transfer clock resumes running as soon as an "L" single is applied to the CTS pin.
Data is set in the UiTB register
Data is transferred from the UiTB register to the UARTi transmit register
CTSi
"L" Start bit Parity bit
D1 D2 D3 D4 D5 D6 D7 P SP
Stop bit
ST D0 D1 D2 D3
Pulse stops because the TE bit is set to "0"
ST D0 D1
TXDi
TXEPT bit in UiC0 register IR bit in SiTIC register
i=0 to 2 "1" "0" "1" "0"
ST
D0
D4
D5
D6
D7
P
SP
Set to "0" by an interrupt request acknowledgement or by program TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO) fEXT : frequency of UiBRG count source (external clock) n : value set to UiBRG
The above timing diagram applies to the case where the register bits are set as follows: * PRYE bit in UiMR register = 1 (parity enabled) * STPS bit in UiMR register = 0 (1 stop bit) * CRD bit in UiC0 register = 0 (CTS/RTS enabled) and CRS bit = 0 (CTS selected) * UiIRS bit = 1 (an interrupt request occurs when transmit completed): U0IRS bit is bit 0 in UCON register U1IRS bit is bit 1 in UCON register U2IRS bit is bit 4 in U2C1 register
(1) 9-bit Data Transmit Timing (with no parity and 2 stop bits) Tc
Transfer Clock TE bit in UiC1 register TI bit in UiC1 register
"1" "0" "1" "0"
Data is set in the UiTB register
Data is transferred from the UiTB register to the UARTi transmit register
Start bit Stop bit
D1 D2 D3 D4 D5 D6 D7 D8 SP SP
Stop bit
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1
TXDi
TXEPT bit in UiC0 register IR bit in SiTIC register
"1" "0" "1" "0"
ST
D0
Set to "0" by an interrupt request acknowledgement or by program
i=0 to 2
The above timing diagram applies to the case where the register bits are set as follows: * PRYE bit in UiMR register = 0 (parity disabled) * STPS bit in UiMR register = 1 (2 stop bits) * CRD bit in UiC0 register = 1 (CTS/RTS disabled) * UiIRS bit = 0 (an interrupt request occurs when transmit buffer becomes empty): U0IRS bit is bit 0 in UCON register U1IRS bit is bit 1 in UCON register U2IRS bit is bit 4 in U2C1 register
TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO) fEXT : frequency of UiBRG count source (external clock) n : value set to UiBRG
Figure 15.18
Transmit Operation
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* Example of Receive Timing when Transfer Data is 8 Bits Long (parity disabled, one stop bit)
UiBRG count source RE bit in UiC1 register RXDi "1" "0" Start bit Sampled "L" Receive data taken in Transfer clock RI bit in UiC1 register RTSi IR bit in SiRIC register Reception triggered when transfer clock "1" is generated by falling edge of start bit "0" "H" "L" "1" "0" Set to "0" by an interrupt request acknowledgement or by program The above timing diagram applies to the case where the register bits are set as follows: * PRYE bit in UiMR register = 0 (parity disabled) * STPS bit in UiMR register = 0 (1 stop bit) * CRD bit in UiC0 register = 0 (CTSi/RTSi enabled) and CRS bit = 1 (RTSi selected) i = 0 to 2 Transferred from UARTi receive register to UiRB register D0 D1 D7
Stop bit
Figure 15.19
Receive Operation
15.1.2.1
Bit Rate
In UART mode, the frequency set by the UiBRG register (i=0 to 2) divided by 16 become the bit rates. Table 15.9 lists Example of Bit Rates and Settings. Table 15.9 Example of Bit Rates and Settings
Count Source of UiBRG 1200 2400 4800 9600 14400 19200 28800 31250 38400 51200 f8 f8 f8 f1 f1 f1 f1 f1 f1 f1 Peripheral Function Clock : 16MHz Set Value of UiBRG : n 103 (67h) 51 (33h) 25 (19h) 103 (67h) 68 (44h) 51 (33h) 34 (22h) 31 (1Fh) 25 (19h) 19 (13h) Bit Rate (bps) 1202 2404 4808 9615 14493 19231 28571 31250 38462 50000
Bit Rate (bps)
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15.1.2.2
Counter Measure for Communication Error Occurs
If a communication error occurs while transmitting or receiving in UART mode, follow the procedures below. * Resetting the UiRB register (i=0 to 2) (1) Set the RE bit in the UiC1 register to "0" (reception disabled) (2) Set the RE bit in the UiC1 register to "1" (reception enabled) * Resetting the UiTB register (i=0 to 2) (1) Set the SMD2 to SMD0 bits in the UiMR register "000b" (Serial interface disabled) (2) Set the SMD2 to SMD0 bits in the UiMR register "001b", "101b", "110b". (3) "1" is written to RE bit in the UiC1 register (transmission enabled), regardless of the TE bit in the UiCi register
15.1.2.3
LSB First/MSB First Select Function
As shown in Figure 15.20, use the UFORM bit in the UiC0 register to select the transfer format. This function is valid when transfer data is 8 bits long.
(1) When The UFORM Bit in The UiC0 Register = 0 (LSB First)
CLKi TXDi RXDi ST ST D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 P P SP SP
(2) When The UFORM Bit = 1 (MSB First)
CLKi TXDi RXDi ST ST D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 P P SP SP
NOTES : 1. This applies to the case where the CKPOL bit in the UiC0 register = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the UiLCH bit in the UiC1 register = 0 (no reverse), the STPS bit in the UiMR register = 0 (1 stop bit) and the PRYE bit in the UiMR register = 1 (parity enabled).
Figure 15.20 Transfer Format
ST : Start bit P : Parity bit SP : Stop bit i = 0 to 2
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15.1.2.4
Serial Data Logic Switching Function
The data written to the UiTB register has its logic reversed before being transmitted. Similarly, the received data has its logic reversed when read from the UiRB register. Figure 15.21 shows Serial Data Logic Switching.
(1) When the UiLCH bit in the UiC1 Register = 0 (No Reverse)
Transfer Clock TXDi (No Reverse)
"H" "L" "H" "L"
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
(2) When the UiLCH Bit = 1 (Reverse)
Transfer Clock TXDi (Reverse)
"H" "L" "H" "L"
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
NOTES : 1. This applies to the case where the CKPOL bit in the UiC0 register = 0 (transmit data output at the falling edge of the transfer clock), the UFORM bit in the UiC0 register = 0 (LSB first), the STPS bit in the UiMR register = 0 (1 stop bit) and the PRYE bit in the UiMR register = 1 (parity enabled).
Figure 15.21 Serial Data Logic Switching
ST : Start bit P : Parity bit SP : Stop bit i = 0 to 2
15.1.2.5
TXD and RXD I/O Polarity Inverse Function
This function inverses the polarities of the TXDi pin output and RXDi pin input. The logic levels of all input/ output data (including the start, stop and parity bits) are inversed. Figure 15.22 shows the TXD and RXD I/O Polarity Inverse.
(1) When the IOPOL Bit in the UiMR Register = 0 (No Reverse)
Transfer Clock TXDi RXDi
"H" "L" "H"
(No Reverse) "L"
"H"
ST ST
D0 D0
D1 D1
D2 D2
D3 D3
D4 D4
D5 D5
D6 D6
D7 D7
P P
SP SP
(No Reverse) "L"
(2) When the IOPOL Bit = 1 (Reverse)
Transfer Clock TXDi
(Reverse)
"H" "L" "H" "L" "H"
ST ST
D0 D0
D1 D1
D2 D2
D3 D3
D4 D4
D5 D5
D6 D6
D7 D7
P P
SP SP ST : Start bit P : Parity bit SP : Stop bit i = 0 to 2
(Reverse) "L"
RXDi
NOTES : 1. This applies to the case where the UFORM bit in the UiC0 register = 0 (LSB first), the STPS bit in the UiMR register = 0 (1 stop bit) and the PRYE bit in the UiMR register = 1 (parity enabled).
Figure 15.22 TXD and RXD I/O Polarity Inverse
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15.1.2.6
CTS/RTS Function
When the CTS function is used transmit operation start when "L" is applied to the CTSi/RTSi (i=0 to 2) pin. Transmit operation begins when the CTSi/RTSi pin is held "L". If the "L" signal is switched to "H" during a transmit operation, the operation stops before the next data. When the RTS function is used, the CTSi/RTSi pin outputs on "L" signal when the microcomputer is ready to receive. The output level becomes "H" on the first falling edge of the CLKi pin. * CRD bit in UiC0 register = 1 (disable CTS/RTS function of UART0) CTSi/RTSi pin is programmable I/O function * CRD bit = 0, CRS bit = 0 (CTS function is selected) CTSi/RTSi pin is CTS function * CRD bit = 0, CRS bit = 1 (RTS function is selected) CTSi/RTSi pin is RTS function
15.1.2.7
CTS/RTS Separate Function (UART0)
This function separates CTS0/RTS0, outputs RTS0 from the P6_0 pin, and accepts as input the CTS0 from the P6_4 pin. To use this function, set the register bits as shown below. * CRD bit in U0C0 register = 0 (enable CTS/RTS of UART0) * CRS bit in U0C0 register = 1 (output RTS of UART0) * CRD bit in U1C0 register = 0 (enable CTS/RTS of UART1) * CRS bit in U1C0 register = 0 (input CTS of UART1) * RCSP bit in UCON register = 1 (inputs CTS0 from the P6_4 pin) * CLKMD1 bit in UCON register = 0 (CLKS1 not used) Note that when using the CTS/RTS separate function, CTS/RTS of UART1 separate function cannot be used.
Microcomputer
TXD0 (P6_3) RXD0 (P6_2) IN OUT
IC
RTS0 (P6_0) CTS0 (P6_4)
CTS RTS
Figure 15.23
CTS/RTS Separate Function
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15.1.3
Special Mode 1 (I2C mode)
I2C mode is provided for use as a simplified I2C interface compatible mode. Table 15.10 lists the specifications of the I2C mode. Table 15.11 to 15.12 lists the registers used in the I2C mode and the register values set. Table 15.13 lists the I2C Mode Functions. Figure 15.24 shows the block diagram for I2C mode. Figure 15.25 shows Transfer to UiRB Register and Interrupt Timing. As shown in Table 15.13, the microcomputer is placed in I2C mode by setting the SMD2 to SMD0 bits to "010b" and the IICM bit to "1". Because SDAi transmit output has a delay circuit attached, SDAi output does not change state until SCLi goes low and remains stably low. Table 15.10 I2C Mode Specifications
Specification Transfer data length: 8 bits * During master CKDIR bit in the UiMR (i=0 to 2) register = 0 (internal clock) : fj/ (2(n+1)) fj = f1SIO, f2SIO, f8SIO, f32SIO n: Setting value of UiBRG register 00h to FFh * During slave CKDIR bit = 1 (external clock) : Input from SCLi pin Before transmission can start, the following requirements must be met (1) * The TE bit in the UiC1 register= 1 (transmission enabled) * The TI bit in the UiC1 register = 0 (data present in UiTB register) Before reception can start, the following requirements must be met (1) * The RE bit in UiC1 register= 1 (reception enabled) * The TE bit in UiC1 register= 1 (transmission enabled) * The TI bit in UiC1 register= 0 (data present in the UiTB register) When start or stop condition is detected, acknowledge undetected, and acknowledge detected Overrun error (2) This error occurs if the serial interface started receiving the next data before reading the UiRB register and received the 8th bit of the next data * Arbitration lost Timing at which the ABT bit in the UiRB register is updated can be selected * SDAi digital delay No digital delay or a delay of 2 to 8 UiBRG count source clock cycles selectable * Clock phase setting With or without clock delay selectable
Item Transfer Data Format Transfer Clock
Transmission Start Condition Reception Start Condition
Interrupt Request Generation Timing Error Detection
Select Function
NOTES: 1. When an external clock is selected, the conditions must be met while the external clock is in the high state. 2. If an overrun error occurs, bits 8 to 0 in the UiRB register are undefined. The IR bit in the SiRIC register does not change to "1" (interrupt requested).
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SDAi Delay circuit
Start and stop condition generation block STSPSEL=1 STSPSEL=0 ACK=0 SDHI ACKD register
DQ T
SDA(STSP) SCL(STSP)
IICM2=1
DMA0, DMA1 request (UART1: DMA0 only)
ACK=1
Transmission register UARTi ALS
IICM=1 and IICM2=0
UARTi transmit, NACK interrupt request
Arbitration
IICM2=1
DMA0 (UART0, UART2)
Noise Filter
Reception register UARTi
IICM=1 and IICM2=0
UARTi receive, ACK interrupt request, DMA1 request
Start condition detection
S R Q
Bus busy
NACK
Stop condition detection
DQ T DQ T
SCLi
Falling edge detection IICM=0 I/O port STSPSEL=0
Q R
Port
register(1)
ACK
9th bit Internal clock CLK control UARTi
R S
Noise Filter
SWC2 IICM=1 UARTi STSPSEL=1 External clock
Start/stop condition detection interrupt request
9th bit falling edge SWC
This diagram applies to the case where the SMD2 to SMD0 bits in the UiMR register = 010b and the IICM bit in the UiSMR register = 1. IICM : Bit in UiSMR register IICM2, SWC, ALS, SWC2, SDHI : Bit in UiSMR2 register STSPSEL, ACKD, ACKC : Bit in UiSMR4 register i=0 to 2 NOTES : 1. If the IICM bit = 1, the pin can be read even when the PD6_2, PD6_6 or PD7_1 bit = 1 (output mode).
Figure 15.24
I2C Mode Block Diagram
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Table 15.11
Register UiTB UiRB (3)
Registers to Be Used and Settings in I2C Mode (1)
Bit 0 to 7 0 to 7 8 ABT OER 0 to 7 SMD2 to SMD0 CKDIR IOPOL CLK1, CLK0 CRS TXEPT CRD (4) NCH CKPOL UFORM TE TI RE RI U2IRS (1) U2RRM (1), UiLCH, UiERE IICM ABC BBS 3 to 7 IICM2 CSC SWC Function Master Slave Set transmission data Set transmission data Reception data can be read Reception data can be read ACK or NACK is set in this bit ACK or NACK is set in this bit Arbitration lost detection flag Invalid Overrun error flag Overrun error flag Set a bit rate Invalid Set to "010b" Set to "010b" Set to "0" Set to "1" Set to "0" Set to "0" Select the count source for the UiBRG Invalid register Invalid because CRD = 1 Invalid because CRD = 1 Transmit buffer empty flag Transmit buffer empty flag Set to "1" Set to "1" Set to "1" (2) Set to "1" (2) Set to "0" Set to "0" Set to "1" Set to "1" Set this bit to "1" to enable transmission Set this bit to "1" to enable transmission Transmit buffer empty flag Transmit buffer empty flag Set this bit to "1" to enable reception Set this bit to "1" to enable reception Reception complete flag Reception complete flag Invalid Invalid Set to "0" Set to "0" Set to "1" Select the timing at which arbitration-lost is detected Bus busy flag Set to "0" See Table 15.13 I2C Mode Functions Set this bit to "1" to enable clock synchronization Set this bit to "1" to have SCLi output fixed to "L" at the falling edge of the 9th bit of clock Set this bit to "1" to have SDAi output stopped when arbitration-lost is detected Set to "0" Set this bit to "1" to have SCLi output forcibly pulled low Set this bit to "1" to disable SDAi output Set to "0" Set to "1" Invalid Bus busy flag Set to "0" See Table 15.13 I2C Mode Functions Set to "0" Set this bit to "1" to have SCLi output fixed to "L" at the falling edge of the 9th bit of clock Set to "0" Set this bit to "1" to initialize UARTi at start condition detection Set this bit to "1" to have SCLi output forcibly pulled low Set this bit to "1" to disable SDAi output Set to "0"
UiBRG UiMR (3)
UiC0
UiC1
UiSMR
UiSMR2
ALS STAC SWC2 SDHI 7
NOTES: 1. Set the bit 4 and bit 5 in the U0C1 and U1C1 register to "0". The U0IRS, U1IRS, U0RRM and U1RRM bits are in the UCON register. 2. TXD2 pin is N channel open-drain output. No NCH bit in the U2C0 register is assigned. When write, set to "0". 3. Not all register bits are described above. Set those bits to "0" when writing to the registers in I2C mode. 4. When using UART1 in I2C mode and enabling the CTS/RTS separate function of UART0, set the CRD bit in the U1C0 register to "0" (CTS/RTS enable) and the CRS bit to "0" (CTS input). i=0 to 2
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Table 15.12
Register UiSMR3
Registers to Be Used and Settings in I2C Mode (2)
Bit Master 0, 2, 4 and NODC CKPH DL2 to DL0 STAREQ RSTAREQ STPREQ STSPSEL ACKD ACKC SCLHI SWC9 Set to "0" See Table 15.13 I2C Mode Functions Set the amount of SDAi digital delay Set this bit to "1" to generate start condition Set this bit to "1" to generate restart condition Set this bit to "1" to generate stop condition Set this bit to "1" to output each condition Select ACK or NACK Set this bit to "1" to output ACK data Set this bit to "1" to have SCLi output stopped when stop condition is detected Set to "0" Set to "1" Invalid Set to "0" Set to "0" Set to "0" Set to "0" Set to "0" Function Slave Set to "0" See Table 15.13 I2C Mode Functions Set the amount of SDAi digital delay Set to "0" Set to "0" Set to "0" Set to "0" Select ACK or NACK Set this bit to "1" to output ACK data Set to "0" Set this bit to "1" to set the SCLi to "L" hold at the falling edge of the 9th bit of clock Set to "1" Invalid Set to "0" Set to "0" Set to "0" Set to "0" Set to "0"
UiSMR4
IFSR2A UCON
IFSR26, ISFR27 U0IRS, U1IRS U0RRM, U1RRM CLKMD0 CLKMD1 RCSP 7
i=0 to 2
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Table 15.13
Function
I2C Mode Functions
Clock Synchronous Serial I/O Mode (SMD2 to SMD0 = 001b, IICM = 0) I2C Mode (SMD2 to SMD0 = 010b, IICM = 1) IICM2 = 0 (NACK/ACK interrupt) CKPH = 0 (No clock delay) CKPH = 1 (Clock delay) IICM2 = 1 (UART transmit/receive interrupt) CKPH = 0 (No clock delay) CKPH = 1 (Clock delay)
Factor of Interrupt Number 6, 7 and 10 (1, 5, 7) Factor of Interrupt Number 15, 17 and 19 (1, 6) Factor of Interrupt Number 16, 18 and 20 (1, 6)
-
Start condition detection or stop condition detection (See Table 15.14 STSPSEL Bit Functions) No acknowledgment detection (NACK) Rising edge of SCLi 9th bit Acknowledgment detection (ACK) Rising edge of SCLi 9th bit UARTi transmission Rising edge of SCLi 9th bit UARTi transmission Falling edge of SCLi next to the 9th bit
UARTi transmission Transmission started or completed (selected by UiIRS) UARTi reception When 8th bit received CKPOL = 0 (rising edge) CKPOL = 1 (falling edge) CKPOL = 0 (rising edge) CKPOL = 1 (falling edge)
UARTi reception Falling edge of SCLi 9th bit
Timing for Transferring Data From the UART Reception Shift Register to the UiRB Register UARTi Transmission Output Delay Functions of P6_3, P6_7 and P7_0 Pins Functions of P6_2, P6_6 and P7_1 Pins Functions of P6_1, P6_5 and P7_2 Pins Noise Filter Width Read RXDi and SCLi Pin Levels Initial Value of TXDi and SDAi Outputs DMA1 Factor (6) Store Received Data
Rising edge of SCLi 9th bit
Falling edge of SCLi 9th bit
Falling and rising edges of SCLi 9th bit
Not delayed TXDi output RXDi input CLKi input or output selected 15ns Possible when the corresponding port direction bit = 0 CKPOL = 0 (H) CKPOL = 1 (L) UARTi reception 1st to 8th bits of the received data are stored into bits 7 to 0 in the UiRB register
Delayed SDAi input/output SCLi input/output
- (Cannot be used in I2C mode)
200ns Always possible no matter how the corresponding port direction bit is set The value set in the port register before setting I2C mode (2) H L H L
Initial and End Values of SCLi -
Acknowledgment detection (ACK) 1st to 8th bits of the received data are stored into bits 7 to 0 in the UiRB register
UARTi reception Falling edge of SCLi 9th bit 1st to 7th bits of the received data are stored into bits 6 to 0 in the UiRB register. 8th bit is stored into bit 8 in the UiRB register. 1st to 8th bits are stored into bits 7 to 0 in the UiRB register (3)
Read Received Data
The UiRB register status is read
Bits 6 to 0 in the UiRB register (4) are read as bits 7 to 1. Bit 8 in the UiRB register is read as bit 0.
NOTES: 1. If the source or factor of any interrupt is changed, the IR bit in the interrupt control register for the changed interrupt may inadvertently be set to "1" (interrupt requested). (Refer to 22.6 Precautions for Interrupt) If one of the bits shown below is changed, the interrupt source, the interrupt timing, etc. change. Therefore, always be sure to clear the IR bit to "0" (interrupt not requested) after changing those bits. SMD2 to SMD0 bits in the UiMR register, IICM bit in the UiSMR register, IICM2 bit in the UiSMR2 register, CKPH bit in the UiSMR3 register 2. Set the initial value of SDAi output while the SMD2 to SMD0 bits in the UiMR register = 000b (serial interface disabled). 3. Second data transfer to UiRB register (Rising edge of SCLi 9th bit) 4. First data transfer to UiRB register (Falling edge of SCLi 9th bit) 5. See Figure 15.27 STSPSEL Bit Functions. 6. See Figure 15.25 Transfer to UiRB Register and Interrupt Timing. 7. When using UART0, be sure to set the IFSR26 bit in the IFSR2A register to "1" (factor of interrupt: UART0 bus collision). When using UART1, be sure to set the IFSR27 bit to "1" (factor of interrupt: UART1 bus collision). i = 0 to 2
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(1) IICM2= 0 (ACK and NACK interrupts), CKPH= 0 (no clock delay)
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit
SCLi SDAi
D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK, NACK)
ACK interrupt (DMA1 request), NACK interrupt Transfer to UiRB register
b15 *** b9 b8 D8 b7 D7 D6 D5 D4 D3 D2 D1 b0 D0
UiRB register
(2) IICM2= 0, CKPH= 1 (clock delay)
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit
SCLi SDAi
D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK, NACK)
ACK interrupt (DMA1 request), NACK interrupt Transfer to UiRB register
b15 *** b9 b8 D8 b7 D7 D6 D5 D4 D3 D2 D1 b0 D0
UiRB register
(3) IICM2= 1 (UART transmit/receive interrupt), CKPH= 0
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit
SCLi SDAi
D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK, NACK)
Receive interrupt (DMA1 request)
Transmit interrupt
Transfer to UiRB register
b15 *** b9 b8 D0 b7 D7 D6 D5 D4 D3 D2 b0 D1
UiRB register
(4) IICM2= 1, CKPH= 1
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit
SCLi SDAi
D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK, NACK)
Receive interrupt (DMA1 request)
Transmit interrupt
Transfer to UiRB register
b15 *** b9 b8 D0 b7 D7 D6 D5 D4 D3 D2 b0 D1
Transfer to UiRB register
b15 *** b9 b8 D8 b7 D7 D6 D5 D4 D3 D2 D1 b0 D0
UiRB register
UiRB register
i=0 to 2 This diagram applies to the case where the following condition is met. * UiMR register CKDIR bit = 0 (Slave selected)
Figure 15.25
Transfer to UiRB Register and Interrupt Timing
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15.1.3.1
Detection of Start and Stop Condition
Whether a start or a stop condition has been detected is determined. A start condition-detected interrupt request is generated when the SDAi pin changes state from high to low while the SCLi pin is in the high state. A stop condition-detected interrupt request is generated when the SDAi pin changes state from low to high while the SCLi pin is in the high state. Because the start and stop condition-detected interrupts share the interrupt control register and vector, check the BBS bit in the UiSMR register to determine which interrupt source is requesting the interrupt.
3 to 6 cycles < duration for setting-up 3 to 6 cycles < duration for holding
(1)
(1)
Duration for setting up
SCLi SDAi
Duration for holding
(Start condition)
SDA i
(Stop condition) i = 0 to 2 NOTES : 1. When the PCLK1 bit in the PCLKR register = 1, this is the cycle number of f1SIO, and the PCLK1 bit = 0, this is the cycle number of f2SIO.
Figure 15.26
Detection of Start and Stop Condition
15.1.3.2
Output of Start and Stop Condition
A start condition is generated by setting the STAREQ bit in the UiSMR4 register (i = 0 to 2) to "1" (start). A restart condition is generated by setting the RSTAREQ bit in the UiSMR4 register to "1" (start). A stop condition is generated by setting the STPREQ bit in the UiSMR4 register to "1" (start). The output procedure is described below. (1) Set the STAREQ bit, RSTAREQ bit or STPREQ bit to "1" (start). (2) Set the STSPSEL bit in the UiSMR4 register to "1" (output). The function of the STSPSEL bit is shown in Table 15.14 and Figure 15.27.
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Table 15.14
STSPSEL Bit Functions
Function Output of SCLi and SDAi Pins
Start/Stop Condition Interrupt Request Generation Timing
STSPSEL = 0 Output of transfer clock and data Output of start/stop condition is accomplished by a program using ports (not automatically generated in hardware) Start/stop condition detection
STSPSEL = 1 Output of a start/stop condition according to the STAREQ, RSTAREQ and STPREQ bit
Finish generating start/stop condition
(1) When Slave CKDIR=1 (external clock) STSPSEL bit SCLi SDAi Start condition detection interrupt (2) When Master CKDIR=0 (internal clock), CKPH=1 (clock delayed) STSPSEL bit
Set to "1" in a program Set to "0" in a program Set to "1" in a program Set to "0" in a program
0 1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit
Stop condition detection interrupt
1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit
SCLi SDAi
Set STAREQ=1 (start)
Set STPREQ=1 Stop condition detection Start condition detection (start) interrupt interrupt
Figure 15.27
STSPSEL Bit Functions
15.1.3.3
Arbitration
Unmatching of the transmit data and SDAi pin input data is checked synchronously with the rising edge of SCLi. Use the ABC bit in the UiSMR register to select the timing at which the ABT bit in the UiRB register is updated. If the ABC bit = 0 (updated bitwise), the ABT bit is set to "1" at the same time unmatching is detected during check, and is cleared to "0" when not detected. In cases when the ABC bit is set to "1", if unmatching is detected even once during check, the ABT bit is set to "1" (unmatching detected) at the falling edge of the clock pulse of 9th bit. If the ABT bit needs to be updated bytewise, clear the ABT bit to "0" (undetected) after detecting acknowledge in the first byte, before transferring the next byte. Setting the ALS bit in the UiSMR2 register to "1" (SDA output stop enabled) factors arbitration-lost to occur, in which case the SDAi pin is placed in the high-impedance state at the same time the ABT bit is set to "1" (unmatching detected).
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15.1.3.4
Transfer Clock
Data is transmitted/received using a transfer clock like the one shown in Figure 15.25 Transfer to UiRB Register and Interrupt Timing. The CSC bit in the UiSMR2 register is used to synchronize the internally generated clock (internal SCLi) and an external clock supplied to the SCLi pin. In cases when the CSC bit is set to "1" (clock synchronization enabled), if a falling edge on the SCLi pin is detected while the internal SCLi is high, the internal SCLi goes low, at which time the value of the UiBRG register is reloaded with and starts counting in the low-level interval. If the internal SCLi changes state from low to high while the SCLi pin is low, counting stops, and when the SCLi pin goes high, counting restarts. In this way, the UARTi transfer clock is comprised of the logical product of the internal SCLi and SCLi pin signal. The transfer clock works from a half period before the falling edge of the internal SCLi 1st bit to the rising edge of the 9th bit. To use this function, select an internal clock for the transfer clock. The SWC bit in the UiSMR2 register allows to select whether the SCLi pin should be fixed to or freed from low-level output at the falling edge of the 9th clock pulse. If the SCLHI bit in the UiSMR4 register is set to "1" (enabled), SCLi output is turned off (placed in the highimpedance state) when a stop condition is detected. Setting the SWC2 bit in the UiSMR2 register = 1 (0 output) makes it possible to forcibly output a low-level signal from the SCLi pin even while sending or receiving data. Clearing the SWC2 bit to "0" (transfer clock) allows the transfer clock to be output from or supplied to the SCLi pin, instead of outputting a low-level signal. If the SWC9 bit in the UiSMR4 register is set to "1" (SCL hold low enabled) when the CKPH bit in the UiSMR3 register = 1, the SCLi pin is fixed to low-level output at the falling edge of the clock pulse next to the 9th. Setting the SWC9 bit = 0 (SCL hold low disabled) frees the SCLi pin from low-level output.
15.1.3.5
SDA Output
The data written to the UiTB register bit 7 to bit 0 (D7 to D0) is sequentially output beginning with D7. The 9th bit (D8) is ACK or NACK. The initial value of SDAi transmit output can only be set when IICM = 1 (I2C mode) and the SMD2 to SMD0 bits in the UiMR register = 000b (Serial interface disabled). The DL2 to DL0 bits in the UiSMR3 register allow to add no delays or a delay of 2 to 8 UiBRG count source clock cycles to SDAi output. Setting the SDHI bit in the UiSMR2 register = 1 (SDA output disabled) forcibly places the SDAi pin in the high-impedance state. Do not write to the SDHI bit synchronously with the rising edge of the UARTi transfer clock. This is because the ABT bit may inadvertently be set to "1" (detected).
15.1.3.6
SDA Input
When the IICM2 bit = 0, the 1st to 8th bits (D7 to D0) of received data are stored in the UiRB register bit 7 to bit 0. The 9th bit (D8) is ACK or NACK. When the IICM2 bit = 1, the 1st to 7th bits (D7 to D1) of received data are stored in the UiRB register bit 6 to bit 0 and the 8th bit (D0) is stored in the UiRB register bit 8. Even when the IICM2 bit = 1, providing the CKPH bit = 1, the same data as when the IICM2 bit = 0 can be read out by reading the UiRB register after the rising edge of the corresponding clock pulse of 9th bit.
15.1.3.7
ACK and NACK
If the STSPSEL bit in the UiSMR4 register is set to "0" (start and stop conditions not generated) and the ACKC bit in the UiSMR4 register is set to "1" (ACK data output), the value of the ACKD bit in the UiSMR4 register is output from the SDAi pin. If the IICM2 bit = 0, a NACK interrupt request is generated if the SDAi pin remains high at the rising edge of the 9th bit of transmit clock pulse. An ACK interrupt request is generated if the SDAi pin is low at the rising edge of the 9th bit of transmit clock pulse. If ACKi is selected for the factor of DMA1 request, a DMA transfer can be activated by detection of an acknowledge.
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15.1.3.8
Initialization of Transmission/Reception
If a start condition is detected while the STAC bit = 1 (UARTi initialization enabled), the serial interface operates as described below. * The transmit shift register is initialized, and the content of the UiTB register is transferred to the transmit shift register. In this way, the serial interface starts sending data synchronously with the next clock pulse applied. However, the UARTi output value does not change state and remains the same as when a start condition was detected until the first bit of data is output synchronously with the input clock. * The receive shift register is initialized, and the serial interface starts receiving data synchronously with the next clock pulse applied. * The SWC bit is set to "1" (SCL wait output enabled). Consequently, the SCLi pin is pulled low at the falling edge of the 9th clock pulse. Note that when UARTi transmission/reception is started using this function, the TI does not change state. Note also that when using this function, the selected transfer clock should be an external clock.
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15.1.4
Special Mode 2
Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are selectable. Table 15.15 lists the Special Mode 2 Specifications. Table 15.16 lists the Registers to Be Used and Settings in Special Mode 2. Figure 15.28 shows Serial Bus Communication Control Example (UART2). Table 15.15 Special Mode 2 Specifications
Specification Transfer data length: 8 bits * Master mode CKDIR bit in UiMR(i=0 to 2) register = 0 (internal clock) : fj/ (2(n+1)) fj = f1SIO, f2SIO, f8SIO, f32SIO n: Setting value of UiBRG register 00h to FFh * Slave mode CKDIR bit = 1 (external clock selected) : Input from CLKi pin Controlled by input/output ports Before transmission can start, the following requirements must be met (1) * The TE bit in UiC1 register= 1 (transmission enabled) * The TI bit in UiC1 register = 0 (data present in UiTB register) Before reception can start, the following requirements must be met (1) * The RE bit in UiC1 register= 1 (reception enabled) * The TE bit in UiC1 register= 1 (transmission enabled) * The TI bit in UiC1 register= 0 (data present in the UiTB register) For transmission, one of the following conditions can be selected * The UiIRS bit in UiC1 register = 0 (transmit buffer empty): when transferring data from the UiTB register to the UARTi transmit register (at start of transmission) * The UiIRS bit =1 (transfer completed): when the serial interface finished sending data from the UARTi transmit register For reception * When transferring data from the UARTi receive register to the UiRB register (at completion of reception) Overrun error (2) This error occurs if the serial interface started receiving the next data before reading the UiRB register and received the 7th bit of the next data * CLK polarity selection Transfer data input/output can be chosen to occur synchronously with the rising or the falling edge of the transfer clock * LSB first, MSB first selection Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can be selected * Continuous receive mode selection Reception is enabled immediately by reading the UiRB register * Switching serial data logic This function reverses the logic value of the transmit/receive dataClock phase setting * Selectable from four combinations of transfer clock polarities and phases
Item Transfer Data Format Transfer Clock
Transmit/Receive Control Transmission Start Condition Reception Start Condition
Interrupt Request Generation Timing
Error Detection
Select Function
NOTES: 1. When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0 register = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the external clock is in the high state; if the CKPOL bit = 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state. 2. If an overrun error occurs, bits 8 to 0 in the UiRB register are undefined. The IR bit in the SiRIC register does not change to "1" (interrupt requested).
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P1_3 P1_2 P9_3 P7_2(CLK2) P7_1(RXD2) P7_0(TXD2) Microcomputer (Master) P7_2(CLK2) P7_1(RXD2) P7_0(TXD2) Microcomputer (Slave)
P9_3 P7_2(CLK2) P7_1(RXD2) P7_0(TXD2) Microcomputer (Slave)
Figure 15.28
Serial Bus Communication Control Example (UART2)
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Table 15.16
Register UiTB (3) UiRB (3) UiBRG UiMR (3)
Registers to Be Used and Settings in Special Mode 2
Bit 0 to 7 0 to 7 OER 0 to 7 SMD2 to SMD0 CKDIR IOPOL CLK1, CLK0 CRS TXEPT CRD NCH CKPOL UFORM TE TI RE RI U2IRS (1) Function Set transmission data Reception data can be read Overrun error flag Set a bit rate Set to "001b" Set this bit to "0" for master mode or "1" for slave mode Set to "0" Select the count source for the UiBRG register Invalid because CRD = 1 Transmit register empty flag Set to "1" Select TXDi pin output format (2) Clock phases can be set in combination with the CKPH bit in the UiSMR3 register
UiC0
Select the LSB first or MSB first
Set this bit to "1" to enable transmission Transmit buffer empty flag Set this bit to "1" to enable reception Reception complete flag Select UART2 transmit interrupt factor
UiC1
U2RRM (1) UiLCH
UiSMR UiSMR2 UiSMR3 UiERE 0 to 7 0 to 7 CKPH NODC 0, 2, 4 to 7 0 to 7 U0IRS, U1IRS U0RRM, U1RRM CLKMD0 CLKMD1, RCSP, 7
Set this bit to "1" to use continuous receive mode Set this bit to "1" to use inverted data logic
Set to "0" Set to "0" Set to "0" Clock phases can be set in combination with the CKPOL bit in the UiC0 register Set to "0" Set to "0" Set to "0" Select UART0 and UART1 transmit interrupt factor
UiSMR4 UCON
Set this bit to "1" to use continuous receive mode
Invalid because CLKMD1 = 0 Set to "0"
NOTES: 1. Set the bit 4 and bit 5 in the U0C0 and U1C1 register to "0". The U0IRS, U1IRS, U0RRM and U1RRM bits are in the UCON register. 2. TXD2 pin is N channel open-drain output. No NCH bit in the U2C0 register is assigned. When write, set to "0". 3. Not all register bits are described above. Set those bits to "0" when writing to the registers in Special Mode 2. i = 0 to 2
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15.1.4.1
Clock Phase Setting Function
One of four combinations of transfer clock phases and polarities can be selected using the CKPH bit in the UiSMR3 register and the CKPOL bit in the UiC0 register. Make sure the transfer clock polarity and phase are the same for the master and salves to be communicated. Figure 15.29 shows the Transmission and Reception Timing in Master Mode (Internal Clock). Figure 15.30 shows the Transmission and Reception Timing (CKPH=0) in Slave Mode (External Clock) while Figure 15.31 shows the Transmission and Reception Timing (CKPH=1) in Slave Mode (External Clock).
"H" Clock output (CKPOL=0, CKPH=0) "L"
Clock output "H" (CKPOL=1, CKPH=0) "L" Clock output "H" (CKPOL=0, CKPH=1) "L"
"H" Clock output (CKPOL=1, CKPH=1) "L"
Data output timing
"H" "L"
D0
D1
D2
D3
D4
D5
D6
D7
Data input timing
Figure 15.29
Transmission and Reception Timing in Master Mode (Internal Clock)
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Slave control input
"H" "L"
"H" Clock input (CKPOL=0, CKPH=0) "L"
Clock input "H" (CKPOL=1, CKPH=0)
"L"
Data output timing
(1)
"H" "L"
D0
D1
D2
D3
D4
D5
D6
D7
Data input timing
Indeterminate
NOTES : 1. UART2 output is an N-channel open drain and must be pulled-up externally.
Figure 15.30
Transmission and Reception Timing (CKPH=0) in Slave Mode (External Clock)
Slave control input
"H" "L"
"H" Clock input (CKPOL=0, CKPH=1) "L"
Clock input "H" (CKPOL=1, CKPH=1) "L"
Data output timing
(1)
"H" "L"
D0
D1
D2
D3
D4
D5
D6
D7
Data input timing
NOTES : 1. UART2 output is an N-channel open drain and must be pulled-up externally.
Figure 15.31
Transmission and Reception Timing (CKPH=1) in Slave Mode (External Clock)
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15. Serial Interface
15.1.5
Special Mode 3 (IE mode)(UART2)
In this mode, one bit of IEBus is approximated with one byte of UART mode waveform. Table 15.17 lists the Registers to Be Used and Settings in IE Mode. Figure 15.32 shows the Bus Collision Detect Function-Related BitsBus Collision Detect Function-Related Bits. If the TXD2 pin output level and RXD2 pin input level do not match, a UART2 bus collision detect interrupt request is generated.
Table 15.17
Register U2TB U2RB (2) U2BRG U2MR
Registers to Be Used and Settings in IE Mode
Bit 0 to 8 0 to 8 OER, FER, PER, SUM 0 to 7 SMD2 to SMD0 CKDIR STPS PRY PRYE IOPOL CLK1, CLK0 CRS TXEPT CRD NCH CKPOL UFORM TE TI RE RI U2IRS U2RRM, U2LCH, U2ERE 0 to 3, 7 ABSCS ACSE SSS 0 to 7 0 to 7 0 to 7 Function Set transmission data Reception data can be read Error flag Set a bit rate Set to "110b" Select the internal clock or external clock Set to "0" Invalid because PRYE=0 Set to "0" Select the TXD/RXD input/output polarity Select the count source for the U2BRG register Invalid because CRD=1 Transmit register empty flag Set to "1" Select TXD2 pin output mode (1) Set to "0" Set to "0" Set this bit to "1" to enable transmission Transmit buffer empty flag Set this bit to "1" to enable reception Reception complete flag Select the source of UART2 transmit interrupt Set to "0" Set to "0" Select the sampling timing at which to detect a bus collision Set this bit to "1" to use the auto clear function of transmit enable bit Select the transmit start condition Set to "0" Set to "0" Set to "0"
U2C0
U2C1
U2SMR
U2SMR2 U2SMR3 U2SMR4
NOTES: 1. TXD2 pin is N channel open-drain output. No NCH bit in the U2C0 register is assigned. When write, set to "0". 2. Not all register bits are described above. Set those bits to "0" when writing to the registers in IE mode.
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(1) The ABSCS Bit in the U2SMR Register (Bus collision detect sampling clock select)
If ABSCS=0, bus collision is determined at the rising edge of the transfer clock
Transfer clock
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP
TXD2 RXD2
Trigger signal is applied to the TA0IN pin
Timer A0
If ABSCS=1, bus collision is determined when timer A0 (one-shot timer mode) underflows.
(2) The ACSE Bit in the U2SMR Register (Auto clear of transmit enable bit) Transfer clock
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP
TXD2 RXD2
IR bit in BCNIC register TE bit in U2C1 register
If ACSE bit = 1 (automatically clear when bus collision occurs), the TE bit is cleared to "0" (transmission disabled) when the IR bit in the BCNIC register= 1 (unmatching detected).
(3) The SSS Bit in the U2SMR Register (Transmit start condition select)
If SSS bit = 0, the serial interface starts sending data one transfer clock cycle after the transmission enable condition is met.
Transfer clock
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP
TXD2
Transmission enable condition is met If SSS bit = 1, the serial interface starts sending data at the rising edge
(1)
of RXD2
CLK2
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP
TXD2 RXD2
(NOTE 2)
NOTES : 1. The falling edge of RXD2 when IOPOL=0; the rising edge of RXD2 when IOPOL =1. 2. The transmit condition must be met before the falling edge (1) of RXD. This diagram applies to the case where IOPOL=1 (reversed).
Figure 15.32
Bus Collision Detect Function-Related Bits
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15. Serial Interface
15.1.6
Special Mode 4 (SIM Mode) (UART2)
Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be implemented, and this mode allows to output a low from the TXD2 pin when a parity error is detected. Table 15.18 lists the SIM Mode Specifications. Table 15.19 lists the Registers to Be Used and Settings in SIM Mode. Table 15.18 SIM Mode Specifications
Specification * Direct format * Inverse format * CKDIR bit in U2MR register = 0 (internal clock) : fi/ (16(n+1)) fi = f1SIO, f2SIO, f8SIO, f32SIO n: Setting value of U2BRG register 00h to FFh * CKDIR bit = 1 (external clock) : fEXT/(16(n+1)) fEXT: Input from CLK2 pin n: Setting value of U2BRG register 00h to FFh Before transmission can start, the following requirements must be met * The TE bit in the U2C1 register = 1 (transmission enabled) * The TI bit in the U2C1 register = 0 (data present in U2TB register) Before reception can start, the following requirements must be met * The RE bit in the U2C1 register = 1 (reception enabled) * Start bit detection * For transmission When the serial interface finished sending data from the U2TB transfer register (U2IRS bit =1) * For reception When transferring data from the UART2 receive register to the U2RB register (at completion of reception) * Overrun error (1) This error occurs if the serial interface started receiving the next data before reading the U2RB register and received the bit one before the last stop bit of the next data * Framing error (3) This error occurs when the number of stop bits set is not detected * Parity error (3) During reception, if a parity error is detected, parity error signal is output from the TXD2 pin. During transmission, a parity error is detected by the level of input to the RXD2 pin when a transmission interrupt occurs * Error sum flag This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered
Item Transfer Data Format Transfer Clock
Transmission Start Condition Reception Start Condition
Interrupt Request Generation Timing (2)
Error Detection
NOTES: 1. If an overrun error occurs, bits 8 to 0 in the U2RB register are undefined. The IR bit in the S2RIC register does not change to "1" (interrupt requested). 2. A transmit interrupt request is generated by setting the U2IRS bit to "1" (transmission complete) and U2ERE bit to "1" (error signal output) in the U2C1 register after reset. Therefore, when using SIM mode, set the IR bit to "0" (no interrupt request) after setting these bits. 3. The timing at which the framing error flag and the parity error flag are set is detected when data is transferred from the UARTi receive register to the UiRB register.
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Table 15.19
Register U2TB (1) U2RB (1) U2BRG U2MR
Registers to Be Used and Settings in SIM Mode
Bit 0 to 7 0 to 7 OER,FER,PER,SUM 0 to 7 SMD2 to SMD0 CKDIR STPS PRY PRYE IOPOL CLK1, CLK0 CRS TXEPT CRD NCH CKPOL UFORM TE TI RE RI U2IRS U2RRM U2LCH U2ERE 0 to 3 0 to 7 0 to 7 0 to 7 Function Set transmission data Reception data can be read Error flag Set a bit rate Set to "101b" Select the internal clock or external clock Set to "0" Set this bit to "1" for direct format or "0" for inverse format Set to "1" Set to "0" Select the count source for the U2BRG register Invalid because CRD = 1 Transmit register empty flag Set to "1" Set to "0" Set to "0" Set this bit to "0" for direct format or "1" for inverse format Set this bit to "1" to enable transmission Transmit buffer empty flag Set this bit to "1" to enable reception Reception complete flag Set to "1" Set to "0" Set this bit to "0" for direct format or "1" for inverse format Set to "1" Set to "0" Set to "0" Set to "0" Set to "0"
U2C0
U2C1
U2SMR (1) U2SMR2 U2SMR3 U2SMR4
NOTES: 1. Not all register bits are described above. Set those bits to "0" when writing to the registers in SIM mode.
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(1) Transmit Timing
Tc
Transfer clock TE bit in U2C1 register TI bit in U2C1 register
"1" "0" "1" "0"
Data is written to the UARTi register
(Note 1)
TXD2
Parity Error signal returned from Receiving end
Start bit
ST D0 D1 D2 D3 D4 D5 D6
Parity bit
D7 P SP
Stop bit
Data is transferred from the UiTB register to the UARi transmit register
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
An "L" signal is applied from the SIM card due to a parity error
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
RXD2 pin level (2)
TXEPT bit in U2C0 "1" register "0" IR bit in S2TIC register
"1" "0"
An interrupt routine detects "H" or "L"
An interrupt routine detects "H" or "L"
The above timing diagram applies to the case where data is transferred in the direct format. * STPS bit in U2MR register = 0 (1 stop bit) * PRY bit in U2MR register = 1 (even) * UFORM bit in U2C0 register = 0 (LSB first) * U2LCH bit in U2C1 register = 0 (no reverse) * U2IRSCH bit in U2C1 register = 1 (transmit is completed)
Set to "0" by an interrupt request acknowledgement or by program TC = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO) fEXT : frequency of U2BRG count source (external clock) n : value set to U2BRG
(2) Receive Timing
Tc
Transfer clock RE bit in U2C1 register
"1" "0"
Transmit Waveform from the Transmitting end
TXD2
Start bit
ST D0 D1 D2 D3 D4 D5 D6
Parity bit
D7 P SP
Stop bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
TxD2 provides "L" output due to a parity error RXD2 pin level (1)
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
RI bit in U2C1 register IR bit in S2RIC register
"1" "0" "1" "0"
Read the U2RB register
The above timing diagram applies to the case where data is transferred in the direct format. * STPS bit in U2MR register = 0 (1 stop bit) * PRY bit in U2MR register = 1 (even) * UFORM bit in U2C0 register = 0 (LSB first) * U2LCH bit in U2C1 register = 0 (no reverse) * U2IRSCH bit in U2C1 register = 1 (transmit is completed)
Set to "0" by an interrupt request acknowledgement or by program TC = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO) fEXT : frequency of U2BRG count source (external clock) n : value set to U2BRG
NOTES: 1. Data transmission starts when BRG overflows after a value is set to the U2TB register on the rising edge of the TI bit. 2. Because the TxD2 and RxD2 pins are connected, a composite waveform, consisting of transmit waveform from the TxD2 pin and parity error signal from the receiving end, is generated. 3. Because the TxD2 and RxD2 pins are connected, a composite waveform, consisting of transmit waveform from the transmitting end and parity error signal from the TxD2 pin, is generated.
Figure 15.33
Transmit and Receive Timing in SIM Mode
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15. Serial Interface
Microcomputer
SIM card TXD2 RXD2
Figure 15.34
SIM Interface Connection
15.1.6.1
Parity Error Signal Output
The parity error signal is enabled by setting the U2ERE bit in the U2C1 register to "1". The parity error signal is output when a parity error is detected while receiving data. This is achieved by pulling the TXD2 output low with the timing shown in Figure 15.35. If the R2RB register is read while outputting a parity error signal, the PER bit is cleared to "0" and at the same time the TXD2 output is returned high. When transmitting, a transmission-finished interrupt request is generated at the falling edge of the transfer clock pulse that immediately follows the stop bit. Therefore, whether a parity signal has been returned can be determined by reading the port that shares the RXD2 pin in a transmission-finished interrupt routine.
Transfer clock RXD2 TXD2 RI bit in U2C1 register
"H" "L" "H" "L" "H" "L" "1" "0"
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
(NOTE 1)
This timing diagram applies to the case where the direct format is implemented. NOTES : 1. The output of microcomputer is in the high-impedance state (pulled up externally).
ST : Start bit P : Even Parity SP : Stop bit
Figure 15.35
Parity Error Signal Output Timing
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15. Serial Interface
15.1.6.2
Format
When direct format, set the PRYE bit in the U2MR register to "1", the PRY bit to "1", the UFORM bit in the U2C0 register to "0" and the U2LCH bit in the U2C1 register to "0". When data are transmitted, data set in the U2TB register are transmitted with the even-numbered parity, starting from D0. When data are received, received data are stored in the U2RB register, starting from D0. The even-numbered parity determines whether a parity error occurs. When inverse format, set the PRYE bit to "1", the PRY bit to "0", the UFORM bit to "1" and the U2LCH bit to "1". When data are transmitted, values set in the U2TB register are logically inversed and are transmitted with the odd-numbered parity, starting from D7. When data are received, received data are logically inversed to be stored in the U2RB register, starting from D7. The odd-numbered parity determines whether a parity error occurs.
(1) Direct format
Transfer clcck TXD2
"H" "L" "H" "L" D0 D1 D2 D3 D4 D5 D6 D7 P P : Even parity
(2) Inverse format
Transfer clcck TXD2
"H" "L" "H" "L" D7 D6 D5 D4 D3 D2 D1 D0 P P : Odd parity
Figure 15.36
SIM Interface Format
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16. A/D Converter
16. A/D Converter
The microcomputer contains one A/D converter circuit based on 10-bit successive approximation method configured with a capacitive-coupling amplifier. The analog inputs share the pins with P10_0 to P10_7, P9_5, P9_6, and P0_0 to P0_7. Similarly, ADTRG input shares the pin with P9_7. Therefore, when using these inputs, make sure the corresponding port direction bits are set to "0" (= input mode). When not using the A/D converter, set the VCUT bit to "0" (= Vref unconnected), so that no current will flow from the VREF pin into the resistor ladder, helping to reduce the power consumption of the chip. The A/D conversion result is stored in the ADi register bits for ANi, and AN0_i pins (i = 0 to 7). Table 16.1 shows the Performance of A/D Converter. Figure 16.1 shows the A/D Converter Block Diagram, and Figures 16.2 and 16.3 show the A/D converter-related registers. Table 16.1 Performance of A/D Converter
Item Performance Method of A/D Conversion Successive approximation (capacitive coupling amplifier) 0V to AVCC (VCC1) Analog input Voltage (1) Operating clock AD (2) fAD/divide-by-2 of fAD/divide-by-3 of fAD/divide-by-4 of fAD/divide-by-6 of fAD/divide-by-12 of fAD Resolution 8-bit or 10-bit (selectable) Integral Nonlinearity Error When AVCC = VREF = 5V * With 8-bit resolution: 2LSB * With 10-bit resolution AN0 to AN7, AN0_0 to AN0_7, ANEX0 and ANEX1 input : 5LSB When AVCC = VREF = 3.3V * With 8-bit resolution: 2LSB * With 10-bit resolution AN0 to AN7, AN0_0 to AN0_7, ANEX0 and ANEX1 input : 7LSB Operating Modes One-shot mode and repeat mode Analog Input Pins 8 pins (AN0 to AN7) + 2 pins (ANEX0 and ANEX1) + 8 pins (AN0_0 to AN0_7) A/D Conversion Start * Software trigger Condition The ADST bit in the ADCON0 register is set to "1" (A/D conversion starts) * External trigger (retriggerable) Input on the ADTRG pin changes state from high to low after the ADST bit is set to "1" (A/D conversion starts) Conversion Speed * Without sample and hold function 8-bit resolution: 49 AD cycles, 10-bit resolution: 59 AD cycles * With sample and hold function 8-bit resolution: 28 AD cycles, 10-bit resolution: 33 AD cycles NOTES: 1. Does not depend on use of sample and hold function. 2. AD frequency must be 10 MHz or less. When sample & hold function is disabled, AD frequency must be 250kHz or more. When sample & hold function is enabled, AD frequency must be 1MHz or more.
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16. A/D Converter
A/D conversion rate selection
0 CKS2 1
1 0 CKS0 0
CKS1
AD
1/2 fAD 1/3
0 1 TRG 0 1
1/2
Software trigger ADTRG VREF AVSS
Trigger
Resistor ladder
1 VCUT
Successive conversion register
ADCON1 register
ADCON0 register
AD0 register (16) AD1 register (16) AD2 register (16) AD3 register (16) AD4 register (16) AD5 register (16) AD6 register (16) AD7 register (16)
Data bus high-order
Decoder for A/D register
ADCON2 register
Data bus low-order
PM00 PM01
Vref
Decoder for channel selection
Comparator VIN
Port P10 group
CH2 to CH0 =000b =001b =010b =011b =100b =101b =110b =111b
Port P0 group
AN0_0 AN0_1 AN0_2 AN0_3 AN0_4 AN0_5 AN0_6 AN0_7
CH2 to CH0 =000b =001b =010b =011b =100b =101b =110b =111b
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
ADGSEL1 to ADGSEL0=00b OPA1 to OPA0=00b
PM01 to PM00=00b ADGSEL1 to ADGSEL0=10b OPA1 to OPA0=00b
PM01 to PM00=00b ADGSEL1 to ADGSEL0=11b OPA1 to OPA0=00b
ADGSEL1 to ADGSEL0=00b OPA1 to OPA0=11b PM01 to PM0=00b ADGSEL1 to ADGSEL0=10b OPA1 to OPA0=11b
ANEX0 ANEX1
OPA0=1 OPA1=1
OPA1 to OPA0 =01b OPA1=1
Figure 16.1
A/D Converter Block Diagram
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16. A/D Converter
A/D Control Register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol ADCON0 Bit Symbol CH0
Address 03D6h Bit Name Analog Input Pin Select Bit
b2 b1 b0
After Reset 000X0XXXb Function 0 0 0 : AN0 is 0 0 1 : AN1 is 0 1 0 : AN2 is 0 1 1 : AN3 is 1 0 0 : AN4 is 1 0 1 : AN5 is 1 1 0 : AN6 is 1 1 1 : AN7 is selected selected selected selected selected selected selected selected RW RW
CH1
RW
CH2
RW
MD0 -- (b4) TRG ADST CKS0
A/D Operation Mode Select Bit 0 : One-shot mode 0 1 : Repeat mode Nothing is assigned. When w rite, set to "0". When read, its content is ndeterminate. Trigger Select Bit A/D Conversion Start Flag Frequency Select Bit 0 0 : Softw are trigger
________
RW -- RW RW RW
1 : ADTRG trigger 0 : A/D conversion disabled 1 : A/D conversion started Refer to NOTE 2 for the ADCON2 Register
NOTES : 1. If the ADCON0 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate.
A/D Control Register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol ADCON1 Symbol -- (b0) -- (b1) -- (b2) BITS CKS1 VCUT OPA0
Address 03D7h
After Reset 00000XXXb RW -- -- -- RW RW RW RW
Address After Reset Nothing is assigned. When w rite, set to "0". When read, its content is indeterminate. Nothing is assigned. When w rite, set to "0". When read, its content is indeterminate. Nothing is assigned. When w rite, set to "0". When read, its content is indeterminate. 8/10-Bit Mode Select Bit Frequency Select Bit 1 Vref Connect Bit (2) External Op-Amp Connection Mode Bit 0 : 8-bit mode 1 : 10-bit mode Refer to NOTE 2 for the ADCON2 Register 0 : Vref not connected 1 : Vref connected
b7 b6
OPA1
0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A/D converted 1 0 : ANEX1 input is A/D converted 1 1 : Do not set
RW
NOTES : 1. If the ADCON1 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate. 2. If the VCUT bit is reset from "0" (Vref unconnected) to "1" (Vref connected), w ait for 1 s or more before starting A/D conversion.
Figure 16.2
ADCON0 to ADCON1 Registers
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16. A/D Converter
A/D Control Register 2 (1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol ADCON2 Bit Symbol SMP -- (b1) ADGSEL1 -- (b3)
Address 03D4h Bit Name
After Reset XXX00000b Function RW RW -- RW RW
A/D Conversion Method Select 0 : Without sample and hold Bit 1 : With sample and hold Nothing is assigned. When w rite, set to "0". When read, its content is indeterminate. A/D Input Group Select Bit Reserved Bit Frequency Select Bit 2 (2) 0 : Port P10 group is selected 1 : Port P0 group is selected Set to "0" 0: Selects fAD, fAD divided by 2, or fAD divided by 4. 1: Selects fAD divided by 3, fAD divided by 6, or fAD divided by 12.
CKS2
RW
-- (b7-b5)
Nothing is assigned. When w rite, set to "0". When read, their contents are "0".
--
NOTES : 1. If the ADCON2 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate. 2. The OAD frequency must be 10 MHz or less. The selected OAD frequency is determined by a combination of the CKS0 bit in the ADCON0 register, the CKS1 bit in the ADCON1 register, and the CKS2 bit in the ADCON2 register. CKS2 0 0 0 0 1 1 1 1 CKS1 0 0 1 1 0 0 1 1 CKS0 0 1 0 1 0 1 0 1 OAD Divide-by-4 of fAD Divide-by-2 of fAD fAD Ddivide-by-12 of fAD Divide-by-6 of fAD Divide-by-3 of fAD
A/D Register i (i=0 to 7)
Symbol AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Address 03C1h to 03C0h 03C3h to 03C2h 03C5h to 03C4h 03C7h to 03C6h 03C9h to 03C8h 03CBh to 03CAh 03CDh to 03CCh 03CFh to 03CEh After Reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate
(b15) b7
(b8) b0 b7
b0
Function When the BITS bit in the ADCON1 register is "1" (10-bit mode) Eight low -order bits of A/D conversion result Tw o high-order bits of A/D conversion result When the BITS bit is "0" (8-bit mode) A/D conversion result When read, the content is indeterminate
RW RW RO RO --
Nothing is assigned. When w rite, set to "0". When read, their contents are "0".
Figure 16.3
ADCON2 and AD0 to AD7 Registers
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16. A/D Converter
16.1 16.1.1
Mode Description One-Shot Mode
In one-shot mode, analog voltage applied to a selected pin is converted to a digital code once. Table 16.2 shows the One-Shot Mode Specifications. Figures 16.4 and 16.5 shows the ADCON0 and ADCON1 registers in oneshot mode. Table 16.2 One-Shot Mode Specifications
Item Function
A/D Conversion Start Condition
A/D Conversion Stop Condition
Interrupt Request Generation Timing Analog Input Pin Select one pin from AN0 to AN7, AN0_0 to AN0_7, ANEX0 to ANEX1 Reading of Result of A/D Read one of the AD0 to AD7 registers that corresponds to the selected pin Converter
Specification The CH2 to CH0 bits in the ADCON0 register, the ADGSEL1 to ADGSEL0 bits in the ADCON2 register and the OPA1 to OPA0 bits in the ADCON1 register select a pin. Analog voltage applied to the pin is converted to a digital code once. * When the TRG bit in the ADCON0 register is "0" (software trigger) The ADST bit in the ADCON0 register is set to "1" (A/D conversion starts) * When the TRG bit is "1" (ADTRG trigger) Input on the ADTRG pin changes state from high to low after the ADST bit is set to "1" (A/D conversion starts) * Completion of A/D conversion (If a software trigger is selected, the ADST bit is cleared to "0" (A/D conversion halted)) * Set the ADST bit to "0" Completion of A/D conversion
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A/D Control Register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol ADCON0 Bit Symbol CH0
Address 03D6h Bit Name Analog Input Pin Select Bit (2, 3)
b2 b1 b0
After Reset 000X0XXXb Function 0 0 0 : AN0 is 0 0 1 : AN1 is 0 1 0 : AN2 is 0 1 1 : AN3 is 1 0 0 : AN4 is 1 0 1 : AN5 is 1 1 0 : AN6 is 1 1 1 : AN7 is selected selected selected selected selected selected selected selected RW RW
CH1
RW
CH2 A/D Operation Mode Select Bit 0 (3)
RW
MD0 -- (b4) TRG ADST CKS0
0 : One-shot mode
RW -- RW RW RW
Nothing is assigned. When w rite, set to "0". When read, its content is indeterminate. Trigger Select Bit A/D Conversion Start Flag Frequency Select Bit 0 0 : Softw are trigger
_________
1 : ADTRG trigger 0 : A/D conversion disabled 1 : A/D conversion started Refer to NOTE 2 for the ADCON2 Register
NOTES : 1. If the ADCON0 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate. 2. AN0_0 to AN0_7 can be used in the same w ay as AN0 to AN7. Use the ADGSEL1 to ADGSEL0 bits in the ADCON2 register to select the desired pin. 3. After rew riting the MD0 bit, set the CH2 to CH0 bits over again using another instruction.
Figure 16.4
ADCON0 Register (One-shot Mode)
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16. A/D Converter
A/D Control Register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
1
Symbol ADCON1 Symbol -- (b0) -- (b1) -- (b2) BITS CKS1 VCUT OPA0
Address 03D7h
After Reset 00000XXXb RW -- -- -- RW RW RW RW
Address After Reset Nothing is assigned. When w rite, set to "0". When read, its content is indeterminate. Nothing is assigned. When w rite, set to "0". When read, its content is indeterminate. Nothing is assigned. When w rite, set to "0". When read, its content is indeterminate. 8/10-Bit Mode Select Bit Frequency Select Bit 1 Vref Connect Bit (2) External Op-Amp Connection Mode Bit 0 : 8-bit mode 1 : 10-bit mode Refer to NOTE 2 for the ADCON2 Register 1 : Vref connected
b7 b6
OPA1
0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A/D converted 1 0 : ANEX1 input is A/D converted 1 1 : Do not set
RW
NOTES : 1. If the ADCON1 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate. 2. If the VCUT bit is reset from "0" (Vref unconnected) to "1" (Vref connected), w ait for 1 s or more before starting A/D conversion.
Figure 16.5
ADCON1 Register (One-shot Mode)
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16. A/D Converter
16.1.2
Repeat Mode
In repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code. Table 16.3 shows the Repeat Mode Specifications. Figures 16.6 and 16.7 shows the ADCON0 to ADCON1 registers in repeat mode. Table 16.3 Repeat Mode Specifications
Item Function
A/D Conversion Start Condition
A/D Conversion Stop Condition Interrupt Request None generated Generation timing Analog Input Pin Select one pin from AN0 to AN7, AN0_0 to AN0_7, ANEX0 to ANEX1 Reading of Result of A/D Read one of the AD0 to AD7 registers that corresponds to the selected pin Converter
Specification The CH2 to CH0 bits in the ADCON0 register, the ADGSEL1 to ADGSEL0 bits in the ADCON2 register and the OPA1 to OPA0 bits in the ADCON1 register select a pin. Analog voltage applied to this pin is repeatedly converted to a digital code. * When the TRG bit in the ADCON0 register is "0" (software trigger) The ADST bit in the ADCON0 register is set to "1" (A/D conversion starts) * When the TRG bit is "1" (ADTRG trigger) Input on the ADTRG pin changes state from high to low after the ADST bit is set to "1" (A/D conversion starts) Set the ADST bit to "0" (A/D conversion halted)
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16. A/D Converter
A/D Control Register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
1
Symbol ADCON0 Bit Symbol CH0
Address 03D6h Bit Name Analog Input Pin Select Bit (2, 3)
b2 b1 b0
After Reset 000X0XXXb Function 0 0 0 : AN0 is 0 0 1 : AN1 is 0 1 0 : AN2 is 0 1 1 : AN3 is 1 0 0 : AN4 is 1 0 1 : AN5 is 1 1 0 : AN6 is 1 1 1 : AN7 is selected selected selected selected selected selected selected selected RW RW
CH1
RW
CH2 A/D Operation Mode Select Bit 0 (3)
RW
MD0 -- (b4) TRG ADST CKS0
1 : Repeat mode
RW -- RW RW RW
Nothing is assigned. When w rite, set to "0". When read, its content is indeterminate. Trigger Select Bit A/D Conversion Start Flag Frequency Select Bit 0 0 : Softw are trigger
_________
1 : ADTRG trigger 0 : A/D conversion disabled 1 : A/D conversion started Refer to NOTE 2 for the ADCON2 Register
NOTES : 1. If the ADCON0 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate. 2. AN0_0 to AN0_7 can be used in the same w ay as AN0 to AN7. Use the ADGSEL1 to ADGSEL0 bits in the ADCON2 register to select the desired pin. 3. After rew riting the MD0 bit, set the CH2 to CH0 bits over again using another instruction.
Figure 16.6
ADCON0 Register (Repeat Mode)
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16. A/D Converter
A/D Control Register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
1
Symbol ADCON1 Symbol -- (b0) -- (b1) -- (b2) BITS CKS1 VCUT OPA0
Address 03D7h
After Reset 00000XXXb RW -- -- -- RW RW RW RW
Address After Reset Nothing is assigned. When w rite, set to "0". When read, its content is indeterminate. Nothing is assigned. When w rite, set to "0". When read, its content is indeterminate. Nothing is assigned. When w rite, set to "0". When read, its content is indeterminate. 8/10-Bit Mode Select Bit Frequency Select Bit 1 Vref Connect Bit (2) External Op-Amp Connection Mode Bit 0 : 8-bit mode 1 : 10-bit mode Refer to NOTE 2 for the ADCON2 Register 1 : Vref connected
b7 b6
OPA1
0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A/D converted 1 0 : ANEX1 input is A/D converted 1 1 : Do not set
RW
NOTES : 1. If the ADCON1 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate. 2. If the VCUT bit is reset from "0" (Vref unconnected) to "1" (Vref connected), w ait for 1 s or more before starting A/D conversion.
Figure 16.7
ADCON1 Register (Repeat Mode)
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16. A/D Converter
16.2 16.2.1
Function Resolution Select Function
The desired resolution can be selected using the BITS bit in the ADCON1 register. If the BITS bit is set to "1" (10-bit conversion accuracy), the A/D conversion result is stored in the bit 0 to bit 9 in the ADi register (i = 0 to 7). If the BITS bit is set to "0" (8-bit conversion accuracy), the A/D conversion result is stored in the bit 0 to bit 7 in the ADi register.
16.2.2
Sample and Hold
If the SMP bit in the ADCON2 register is set to "1" (with sample-and-hold), the conversion speed per pin is increased to 28 AD cycles for 8-bit resolution or 33 AD cycles for 10-bit resolution. Sample and Hold is effective in all operation modes. Select whether or not to use the Sample and Hold function before starting A/D conversion.
16.2.3
Extended Analog Input Pins
In one-shot and repeat modes, the ANEX0 and ANEX1 pins can be used as analog input pins. Use the OPA1 to OPA0 bits in the ADCON1 register to select whether or not use ANEX0 and ANEX1. The A/D conversion results of ANEX0 and ANEX1 inputs are stored in the AD0 and AD1 registers, respectively.
16.2.4
Current Consumption Reducing Function
When not using the A/D converter, its resistor ladder and reference voltage input pin (VREF) can be separated using the VCUT bit in the ADCON1 register. When separated, no current will flow from the VREF pin into the resistor ladder, helping to reduce the power consumption of the chip. To use the A/D converter, set the VCUT bit to "1" (Vref connected) and then set the ADST bit in the ADCON0 register to "1" (A/D conversion start). The VCUT and ADST bits cannot be set to "1" at the same time. Nor can the VCUT bit be set to "0" (Vref unconnected) during A/D conversion.
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16. A/D Converter
16.2.5
Output Impedance of Sensor under A/D Conversion
To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 16.8 has to be completed within a specified period of time. T (sampling time) as the specified time. Let output impedance of sensor equivalent circuit be R0, microcomputer's internal resistance be R, precision (error) of the A/D converter be X, and the A/D converter's resolution be Y (Y is 1024 in the 10-bit mode, and 256 in the 8-bit mode). 1 - -------------------------- t C ( R0 + R ) VC = VIN 1 - e VC is generally X X VC = VIN - --- VIN = VIN 1 - --- Y Y 1 - --------------------------T C ( R0 + R ) = X e --Y 1 X - -------------------------- T = ln --Y C ( R0 + R ) T R0 = - ------------------- - R C * ln X --Y
And when t = T,
Hence,
Figure 16.8 shows Analog Input Pin and External Sensor Equivalent Circuit. When the difference between VIN and VC becomes 0.1LSB, we find impedance R0 when voltage between pins VC changes from 0 to VIN-(0.1/ 1024) VIN in time T. (0.1/1024) means that A/D precision drop due to insufficient capacitor charge is held to 0.1LSB at time of A/D conversion in the 10-bit mode. Actual error however is the value of absolute precision added to 0.1LSB. When f(AD) = 10 MHz, T = 0.3 s in the A/D conversion mode with sample & hold. Output impedance R0 for sufficiently charging capacitor C within time T is determined as follows. T = 0.3 s, R = 7.8 k, C = 1.5 pF, X = 0.1, and Y = 1024. Hence, 0.3 x 10 - 6 R0 = - ---------------------------------------------------- - 7.8 x 10 3 = 13.9 x 10 3 0.1 1.5 x 10 - 12 * ln ----------1024 Thus, the allowable output impedance of the sensor circuit capable of thoroughly driving the A/D converter turns out to be approximately 13.9 k.
Microcomputer Sensor equivalent circuit R0 VIN C (1.5pF) VC R (7.8k) Sampling time 3 AD 2 Sample-and-hold function disabled: AD Sample-and-hold function enabled:
Figure 16.8
Analog Input Pin and External Sensor Equivalent Circuit
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17. CRC Calculation
17. CRC Calculation
The Cyclic Redundancy Check (CRC) operation detects an error in data blocks. The microcomputer uses a generator polynomial of CRC_CCITT (X16 + X12 + X5 + 1) to generate CRC code. The CRC code consists of 16 bits which are generated for each data block in given length, separated in 8 bit units. After the initial value is set in the CRCD register, the CRC code is set in that register each time one byte of data is written to the CRCIN register. CRC code generation for one-byte data is finished in two cycles. Figure 17.1 shows the CRC Circuit Block Diagram. Figure 17.2 shows the CRC-related registers. Figure 17.3 shows the calculation example using the CRC operation.
Data bus high-order Data bus low-order
Eight low-order bits CRCD register
Eight high-order bits
CRC code generating circuit
X16 + X12 + X5 + 1
CRCIN register
Figure 17.1
CRC Circuit Block Diagram
CRC Data Register
(b15) b7 (b8) b0 b7 b0
Symbol CRCD Function
Address 03BDh to 03BCh
After Reset Indeterminate Setting Range 0000h to FFFFh RW RW
When data is w ritten to the CRCIN register after setting the initial value in the CRCD register, the CRC code can be read out from the CRCD register.
CRC Input Register
b7 b0
Symbol CRCIN Function Data input
Address 03BEh
After Reset Indeterminate Setting Range 00h to FFh RW RW
Figure 17.2
CRCD and CRCIN Registers
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17. CRC Calculation
Setup procedure and CRC operation when generating CRC code "80C4h"
* CRC operation performed by the M16C CRC code: Remainder of a division in which the value written to the CRCIN register with its bit positions reversed is divided by the generator polynomial Generator polynomial: X16 + X12 + X5 + 1 (1 0001 0000 0010 0001b)
* Setting procedure (1) Reverse the bit positions of the value "80C4h" by program in 1-byte units. "80h" "01h", "C4h" "23h"
b15 b0
(2) Write 0000h (initial value)
CRCD register
b7
b0
(3) Write 01h
CRCIN register Two cycles later, the CRC code for "80h," i.e., 9188h, has its bit positions reversed to become "1189h" which is stored in the CRCD register.
b15 b0
1189h
CRCD register
b7
b0
(4) Write 23h
CRCIN register Two cycles later, the CRC code for "80C4h," i.e., 8250h, has its bit positions reversed to become "0A41h" which is stored in the CRCD register.
b15 b0
0A41h
CRCD register
* Details of CRC operation As shown in (3) above, bit position of "01h" (00000001b) written to the CRCIN register is inversed and becomes "10000000b". Add "1000 0000 0000 0000 0000 0000b", as "10000000b" plus 16 digits, to "0000 0000 0000 0000 0000 0000b", as "0000 0000 0000 0000b" plus 8 digits as the default value of the CRCD register to perform the modulo-2 division. Modulo-2 operation is operation that complies with the law given below. Data 0+0=0 0+1=1 1+0=1 1+1=0 -1 = 1
1000 1000 1 0001 0000 0010 0001 Generator polynomial 1000 0000 0000 1000 1000 0001 1000 0001 1000 1000 1001 CRC code 0000 0000 0000 0001 0001 0000 1 1000 0000 1000 0000 0 1 1000
"0001 0001 1000 1001b (1189h)", the remainder "1001 0001 1000 1000b (9188h)" with inversed bit position, can be read from the CRCD register. When going on to (4) above, "23h (00100011b)" written in the CRCIN register is inversed and becomes "11000100b". Add "1100 0100 0000 0000 0000 0000b", as "11000100b" plus 16 digits, to "1001 0001 1000 1000 0000 0000b", as "1001 0001 1000 1000b" plus 8 digits as a remainder of (3) left in the CRCD register to perform the modulo-2 division. "0000 1010 0100 0001b (0A41h)", the remainder with inversed bit position, can be read from CRCD register.
Figure 17.3
CRC Calculation
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18. Programmable I/O Ports
18. Programmable I/O Ports
The programmable input/output ports (hereafter referred to simply as I/O ports) consist of 87 lines P0 to P10 (except P8_5) for the 100-pin version. Each port can be set for input or output every line by using a direction register, and can also be chosen to be or not be pulled high every 4 lines. P8_5 is an input-only port and does not have a pull-up resistor. Port P8_5 shares the pin with NMI, so that the NMI input level can be read from the P8 register P8_5 bit. Figures 18.1 to 18.5 show the I/O ports. Figure 18.6 shows the I/O Pins. Each pin functions as an I/O port, a peripheral function input/output, or a bus control pin. For details on how to set peripheral functions, refer to each functional description in this manual. If any pin is used as a peripheral function input, set the direction bit for that pin to "0" (input mode). Any pin used as an output pin for peripheral functions output, no matter how the corresponding direction bit is set. When using any pin as a bus control pin, refer to 7.2 Bus Control.
18.1
Port Pi Direction Register (PDi Register, i = 0 to 10)
Figure 18.7 shows the PDi Registers. This register selects whether the I/O port is to be used for input or output. The bits in this register correspond one for one to each port. During memory extension and microprocessor modes, the PDi registers for the pins functioning as bus control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA, and BCLK) cannot be modified. No direction register bit for P8_5 is available.
18.2
Port Pi Register (Pi Register, i = 0 to 10)
Figure 18.8 shows the Pi Registers. Data input/output to and from external devices are accomplished by reading and writing to the Pi register. The Pi register consists of a port latch to hold the input/output data and a circuit to read the pin status. For ports set for input mode, the input level of the pin can be read by reading the corresponding Pi register, and data can be written to the port latch by writing to the Pi register. For ports set for output mode, the port latch can be read by reading the corresponding Pi register, and data can be written to the port latch by writing to the Pi register. The data written to the port latch is output from the pin. The bits in the Pi register correspond one for one to each port. During memory extension and microprocessor modes, the Pi registers for the pins functioning as bus control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA, and BCLK) cannot be modified.
18.3
Pull-up Control Register 0 to Pull-up Control Register 2 (PUR0 to PUR2 Registers)
Figure 18.9 and Figure 18.10 show the PUR0 to PUR2 Registers. The PUR0 to PUR2 registers bits can be used to select whether or not to pull the corresponding port high in 4 bit units. The port chosen to be pulled high has a pull-up resistor connected to it when the direction bit is set for input mode. However, the pull-up control register has no effect on P0 to P3, P4_0 to P4_3, and P5 during memory extension and microprocessor modes. Although the register contents can be modified, no pull-up resistors are connected.
18.4
Port Control Register (PCR Register)
Figure 18.10 shows the PCR Register. When the P1 register is read after setting the PCR0 bit in the PCR register to "1", the corresponding port latch can be read no matter how the PD1 register is set.
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Pull-up selection
Direction register P0_0 to P0_7 (inside dotted-line included)
Data bus P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_4, P5_6 (inside dotted-line not included)
Port latch
(NOTE 1)
Analog input
Pull-up selection
P1_0 to P1_4, P1_7
Direction register
Port P1 control register Port latch
Data bus
(NOTE 1)
Pull-up selection
Direction register P1_5 to P1_6
Port P1 control register Data bus
Port latch
(NOTE 1)
Input to respective peripheral functions
Pull-up selection
P5_7, P6_0, P6_4, P7_3 to P7_6, P8_0, P8_1, P9_0, P9_2
Direction register "1"
Output Data bus Port latch
(NOTE 1)
Input to respective peripheral functions
NOTES: 1.
Symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed VCC.
Figure 18.1
I/O Ports (1)
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18. Programmable I/O Ports
P6_1, P6_5, P7_2
Pull-up selection Direction register
"1"
Output
Data bus
Port latch
Switching between CMOS and Nch
(NOTE 1)
Input to respective peripheral functions
P8_2 to P8_4
Pull-up selection Direction register
Data bus
Port latch (NOTE 1)
Input to respective peripheral functions
P5_5, P7_7, P9_1, P9_3, P9_4, P9_7
Pull-up selection Direction register
Data bus
Port latch (NOTE 1)
Input to respective peripheral functions
NOTES: 1. Symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed VCC.
Figure 18.2
I/O Ports (2)
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18. Programmable I/O Ports
P6_2, P6_6
Pull-up selection Direction register
Data bus
Port latch (NOTE 1)
Switching between CMOS and Nch
Input to respective peripheral functions
Pull-up selection P6_3, P6_7 Direction register
"1" Output
Data bus
Port latch (NOTE 1)
Switching between CMOS and Nch
P8_5
Data bus NMI interrupt input (NOTE 1)
P7_0, P7_1
Direction register
"1"
Output
Data bus
Port latch (NOTE 2)
Input to respective peripheral functions NOTES: 1. Symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed VCC. 2. Symbolizes a parasitic diode.
Figure 18.3
I/O Ports (3)
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18. Programmable I/O Ports
P10_0 to P10_3 (Inside dotted-line not included) P10_4 to P10_7 (Inside dotted-line included)
Pull-up selection Direction register
Data bus
Port latch (NOTE 1)
Analog input Input to respective peripheral functions
Pull-up selection P9_6 Direction register
"1"
Output
Data bus
Port latch (NOTE 1)
Analog input
Pull-up selection P9_5 Direction register
"1"
Data bus
Output
Port latch (NOTE 1)
Input to respective peripheral functions Analog input
NOTES: 1. Symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed VCC.
Figure 18.4
I/O Ports (4)
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18. Programmable I/O Ports
Pull-up selection P8_7 Direction register
Data bus
Port latch (NOTE 1) fC
Rf Pull-up selection P8_6 Direction register
"1" Output
Rd
Data bus
Port latch
(NOTE 1)
NOTES: 1. Symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed VCC.
Figure 18.5
I/O Ports (5)
BYTE BYTE signal input (NOTE 1)
CNVSS CNVSS signal input (NOTE 1)
RESET RESET signal input (NOTE1) NOTES: 1. Symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed VCC1.
Figure 18.6
I/O Pins
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18. Programmable I/O Ports
Port Pi Direction Register (i=0 to 7 and 9 to 10) (1, 2)
b7 b6 b5 b4 b3 b2 b1 b0
After Reset Symbol Address 00h 03E2h, 03E3h, 03E6h, 03E7h PD0 to PD3 00h 03EAh, 03EBh, 03EEh, 03EFh PD4 to PD7 03F3h, 03F6h 00h PD9 to PD10 Bit Name Function Bit Symbol 0 : Input mode PDi_0 Port Pi_0 Direction Bit (Functions as an input port) PDi_1 Port Pi_1 Direction Bit 1 : Output mode PDi_2 Port Pi_2 Direction Bit (Functions as an output port) PDi_3 Port Pi_3 Direction Bit (i = 0 to 7 and 9 to 10) PDi_4 Port Pi_4 Direction Bit PDi_5 Port Pi_5 Direction Bit PDi_6 Port Pi_6 Direction Bit PDi_7 Port Pi_7 Direction Bit
RW RW RW RW RW RW RW RW RW
NOTES : 1. Make sure the PD9 register is w ritten to by the next instruction after setting the PRC2 bit in the PRCR register to "1" (w rite enabled). 2. During memory extension and microprocessor______ _____ PDi register for the pins functioning as bus control pins (A0 modes, the _____ _____ ___ ______ ___ _____ _______ _______ to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY , HOLD, HLDA and BCLK) cannot be modified.
Port P8 Direction Register
b7 b6 b5 b4 b3 b2 b1 b0
After Reset Symbol Address 00X00000b 03F2h PD8 Function Bit Name Bit Symbol Port P8_0 Direction Bit 0 : Input mode PD8_0 (Functions as an input port) Port P8_1 Direction Bit PD8_1 1 : Output mode PD8_2 Port P8_2 Direction Bit (Functions as an output port) PD8_3 Port P8_3 Direction Bit PD8_4 Port P8_4 Direction Bit Nothing is assigned. When w rite, set to "0". -- When read, its content is indeterminate. (b5) PD8_6 PD8_7 Port P8_6 Direction Bit Port P8_7 Direction Bit 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port)
RW RW RW RW RW RW -- RW RW
Figure 18.7
PDi Registers
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18. Programmable I/O Ports
Port Pi Register (i=0 to 7 and 9 to 10) (2)
b7 b6 b5 b4 b3 b2 b1 b0
After Reset Symbol Address Indeterminate 03E0h, 03E1h, 03E4h, 03E5h P0 to P3 Indeterminate 03E8h, 03E9h, 03ECh, 03EDh P4 to P7 03F1h, 03F4h Indeterminate P9 to P10 Bit Name Function Bit Symbol Port Pi_0 Bit The pin level on any I/O port w hich is set for input Pi_0 mode can be read by reading the corresponding bit in this register. Port Pi_1 Bit Pi_1 The pin level on any I/O port w hich is set for output mode can be controlled by w riting to the Port Pi_2 Bit Pi_2 orresponding bit in this register 0 : "L" level Port Pi_3 Bit Pi_3 1 : "H" level (1) (i = 0 to 7 and 9 to 10) Port Pi_4 Bit Pi_4 Pi_5 Pi_6 Pi_7 Port Pi_5 Bit Port Pi_6 Bit Port Pi_7 Bit
RW RW RW RW RW RW RW RW RW
NOTES : 1. Since P7_0 and P7_1 are N-channel open drain ports, the data is high-impedance. 2. During memory extension and___ ______ ___ ______ _____ the Pi_____ _______ the pins functioning as bus control pins (A0 to microprocessor modes, register for _______ _____ _____ A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY , HOLD, HLDA and BCLK) cannot be modified.
Port P8 Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol P8 Bit Symbol P8_0 P8_1 P8_2 P8_3 P8_4 P8_5 P8_6 P8_7
Address 03F0h Bit Name Port P8_0 Bit Port P8_1 Bit Port P8_2 Bit Port P8_3 Bit Port P8_4 Bit Port P8_5 Bit Port P8_6 Bit Port P8_7 Bit
After Reset Indeterminate Function The pin level on any I/O port w hich is set for input mode can be read by reading the corresponding bit in this register. The pin level on any I/O port w hich is set for output mode can be controlled by w riting to the corresponding bit in this register (except for P8_5) 0 : "L" level 1 : "H" level
RW RW RW RW RW RW RO RW RW
Figure 18.8
Pi Registers
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18. Programmable I/O Ports
Pull-up Control Register 0 (2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR0 Bit Symbol PU00 PU01 PU02 PU03 PU04 PU05 PU06 PU07
Address 03FCh Bit Name P0_0 to P0_3 Pull-Up P0_4 to P0_7 Pull-Up P1_0 to P1_3 Pull-Up P1_4 to P1_7 Pull-Up P2_0 to P2_3 Pull-Up P2_4 to P2_7 Pull-Up P3_0 to P3_3 Pull-Up P3_4 to P3_7 Pull-Up 0 : Not pulled high 1 : Pulled high (1)
After Reset 00h Function
RW RW RW RW RW RW RW RW RW
NOTES : 1. The pin for w hich this bit is "1" (pulled high) and the direction bit is "0" (input mode) is pulled high. 2. During memory extension and microprocessor modes, the pins are not pulled high although their corresponding register contents can be modified.
Pull-Up Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR1 Bit Symbol PU10 PU11 PU12 PU13 PU14 PU15 PU16 PU17
Address 03FDh Bit Name P4_0 to P4_3 Pull-Up (3) P4_4 to P4_7 Pull-Up (4) P5_0 to P5_3 Pull-Up (3) P5_4 to P5_7 Pull-Up (3) P6_0 to P6_3 Pull-Up P6_4 to P6_7 Pull-Up P7_2 to P7_3 Pull-Up (1) P7_4 to P7_7 Pull-Up
After Reset (5) 00000000b 00000010b Function 0 : Not pulled high 1 : Pulled high (2)
RW RW RW RW RW RW RW RW RW
NOTES : 1. The P7_0 and P7_1 pins do not have pull-ups. 2. The pin for w hich this bit is "1" (pulled high) and the direction bit is "0" (input mode) is pulled high. 3. During memory extension and microprocessor modes, the pins are not pulled high although the contents of these bits can be modified. 4. If the PM01 to PM00 bits in the PM0 register are set to "01b" (memory expansion mode) or "11b" (microprocessor mode) in a program during single-chip mode, the PU11 bit becomes "1". 5. The values after hardw are reset is as follow s: * 00000000b w hen input on CNVSS pin is "L" * 00000010b w hen input on CNVSS pin is "H" The values after softw are reset is as follow s: * 00000000b w hen PM01 to PM00 bits are "00b" (single-chip mode) * 00000010b w hen PM01 to PM00 bits are "01b" (memory expansion mode) or "11b" (microprocessor mode)
Figure 18.9
PUR0 to PUR1 Registers
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18. Programmable I/O Ports
Pull-Up Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR2 Bit Symbol PU20 PU21 PU22 PU23 PU24 PU25 -- (b7-b6)
Address 03FEh Bit Name P8_0 to P8_3 Pull-Up 0 : Not pulled high 1 : Pulled high (1) P8_4 to P8_7 Pull-Up (2) P9_0 to P9_3 Pull-Up P9_4 to P9_7 Pull-Up P10_0 to P10_3 Pull-Up P10_4 to P10_7 Pull-Up Nothing is assigned. When w rite, set to "0". When read, their contenta are "0".
After Reset 00h Function
RW RW RW RW RW RW RW --
NOTES : 1. The pin for w hich this bit is "1" (pulled high) and the direction bit is "0" (input mode) is pulled high. 2. The P8_5 pin does not have pull-up.
Port Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PCR Bit Symbol
PCR0
After Reset Address 00h 03FFh Bit Name Function Port P1 Control Bit Operation performed w hen the P1 register is read 0 : When the port is set for input, the input levels of P1_0 to P1_7 pins are read. When set for output, the port latch is read. 1 : The port latch is read regardless of w hether the port is set for input or output. Nothing is assigned. When w rite, set to "0". When read, their contents are "0".
RW
RW
-- (b7-b1)
--
Figure 18.10
PUR2 and PCR Registers
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18. Programmable I/O Ports
Table 18.1
Unassigned Pin Handling in Single-chip Mode
Pin Name Ports P0 to P7, P8_0 to P8_4, P8_6 to P8_7, P9 to P10 XOUT (4) NMI (P8_5) AVCC AVSS, VREF, BYTE
Connection After setting for input mode, connect every pin to VSS via a resistor (pulldown); or after setting for output mode, leave these pins open. (1, 2, 3) Open Connect via resistor to VCC (pull-up) Connect to VCC Connect to VSS
NOTES: 1. When setting the port for output mode and leave it open, be aware that the port remains in input mode until it is switched to output mode in a program after reset. For this reason, the voltage level on the pin becomes indeterminate, causing the power supply current to increase while the port remains in input mode. Furthermore, by considering a possibility that the contents of the direction registers could be changed by noise or noise-induced runaway, it is recommended that the contents of the direction registers be periodically reset in software, for the increased reliability of the program. 2. Make sure the unused pins are processed with the shortest possible wiring from the microcomputer pins (within 2 cm). 3. When the ports P7_0 and P7_1 are set for output mode, make sure a low-level signal is output from the pins. The ports P7_0 and P7_1 are N-channel open-drain outputs. 4. With external clock input to XIN pin.
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18. Programmable I/O Ports
Table 18.2
Unassigned Pin Handling in Memory Expansion Mode and Microprocessor Mode
Pin Name
Connection
Ports P0 to P7, After setting for input mode, connect every pin to VSS via a resistor (pullP8_0 to P8_4, P8_6 to P8_7, down); or after setting for output mode, leave these pins open. (1, 2, 3, 4) P9 to P10 P4_4/CS0 to P4_7/CS3 Connect to VCC via a resistor (pulled high) by setting the corresponding direction bit in the PD4 register for CSi (i=0 to 3) to "0" (input mode) and the CSi bit in the CSR register to "0" (chip select disabled). Open Connect via resistor to VCC (pull-up) Connect via resistor to VCC (pull-up) Connect to VCC Connect to VSS
BHE, ALE, HLDA, XOUT (5), BCLK (6) HOLD, RDY NMI (P8_5) AVCC AVSS, VREF
NOTES: 1. When setting the port for output mode and leave it open, be aware that the port remains in input mode until it is switched to output mode in a program after reset. For this reason, the voltage level on the pin becomes indeterminate, causing the power supply current to increase while the port remains in input mode. Furthermore, by considering a possibility that the contents of the direction registers could be changed by noise or noise-induced runaway, it is recommended that the contents of the direction registers be periodically reset in software, for the increased reliability of the program. 2. Make sure the unused pins are processed with the shortest possible wiring from the microcomputer pins (within 2 cm). 3. If the CNVSS pin has the VSS level applied to it, these pins are set for input ports until the processor mode is switched over in a program after reset. For this reason, the voltage levels on these pins become indeterminate, causing the power supply current to increase while they remain set for input ports. 4. When the ports P7_0 and P7_1 are set for output mode, make sure a low-level signal is output from the pins. The ports P7_0 and P7_1 are N-channel open-drain outputs. 5. With external clock input to XIN pin. 6. If the PM07 bit in the PM0 register is set to "1" (BCLK not output), connect this pin to VCC via a resistor (pulled high).
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18. Programmable I/O Ports
Microcomputer
Port P0 to P10 (except for P8_5) (Input mode)
Microcomputer
Port P6 to P10 (except for P8_5) (Input mode)
(Input mode) (Output mode)
(Input mode)
Open
VCC
VCC Port P4_4 / CS0 to P4_7 / CS3
(Output mode)
Open
VCC
NMI NMI XOUT AVCC BYTE AVSS VREF Open VCC BHE HLDA ALE XOUT BCLK (1) HOLD RDY AVCC AVSS VREF VSS VSS
Open
In single-chip mode
In memory expansion mode or in microprocessor mode
NOTES : 1. If the PM07 bit in the PM0 register is set to "1" (BCLK not output), connect this pin to VCC via a resistor (pulled high).
Figure 18.11
Unassigned Pins Handling
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19. Flash Memory Version
19. Flash Memory Version
Aside from the built-in flash memory, the flash memory version microcomputer has the same functions as the masked ROM version. In the flash memory version, the flash memory can perform in three rewrite modes: CPU rewrite mode, standard serial I/O mode and parallel I/O mode. Table 19.1 lists specifications of the flash memory version. See Table 1.1 Performance Outline of M16C/30P Group for the items not listed in Table 19.1. Table 19.1 Flash Memory Version Specifications Item Specification Flash Memory Rewrite Mode 3 modes (CPU rewrite, standard serial I/O, parallel I/O) Erase Block User ROM Area See Figure 19.1 Flash Memory Block Diagram Boot ROM Area 1 block (4 Kbytes) (1) Program Method In units of word Erase Method Block erase Program and Erase Control Method Program and erase controlled by software command Protect Method The lock bit protects each block Number of Commands 8 commands Program and Erase Endurance 100 times (2) Data Retention 10 years ROM Code Protection Parallel I/O and standard serial I/O modes are supported
NOTES: 1. The boot ROM area contains a standard serial I/O mode rewrite control program which is stored in it when shipped from the factory. This area can only be rewritten in parallel input/output mode. 2. Definition of program and erase endurance The programming and erasure times are defined to be per-block erasure times. For example, assume a case where a 4-Kbyte block A is programmed in 2,048 operations by writing one word at a time and erased thereafter. In this case, the block is reckoned as having been programmed and erased once. If a product is 100 times of programming and erasure, each block in it can be erased up to 100 times.
Table 19.2 Flash Memory Rewrite Modes Overview
Standard Serial I/O Mode The user ROM area is rewritten using a dedicated serial programmer. Standard serial I/O mode 1: Clock synchronous serial I/O Standard serial I/O mode 2: UART User ROM area Parallel I/O Mode The boot ROM area and user ROM area is rewritten using a dedicated parallel programmer.
Flash Memory CPU rewrite Mode Rewrite Mode Function The User ROM area is rewritten when the CPU executes software commands. EW0 mode: Rewrite in areas other than flash memory (1) EW1 mode: Can be rewritten in the flash memory Areas which User ROM area can be Rewritten Operating Single-chip mode Mode Memory expansion mode (EW0 mode) Boot mode (EW0 mode) ROM None Programmer
User ROM area Boot ROM area Parallel I/O mode
Boot mode
Serial programmer
Parallel programmer
NOTES: 1. When in CPU mode, the PM10 bit in the PM1 register is set to "1". Execute the rewrite control program in the internal RAM or in an external area usable when the PM10 bit is "1".
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19. Flash Memory Version
19.1
Memory Map
The flash memory contains the user ROM area and the boot ROM area. The user ROM area has space to store the microcomputer operating program in single-chip mode or memory expansion mode and a separate 4-Kbyte space as the block A. Figure 19.1 shows a Flash Memory Block Diagram. The user ROM area is divided into several blocks, each of which can be protected (locked) from program or erase. The user ROM area can be rewritten in CPU rewrite, standard serial I/O and parallel I/O modes. Block A is enabled for use by setting the PM10 bit in the PM1 register to "1" (block A enabled, CS2 area at addresses 10000h to 26FFFh). The boot ROM area is located at the same addresses as the user ROM area. It can only be rewritten in parallel I/O mode (refer to 19.1.1 Boot Mode). A program in the boot ROM area is executed after a hardware reset occurs while an "H" signal is applied to the CNVSS and P5_0 pins and an "L" signal is applied to the P5_5 pin (refer to 19.1.1 Boot Mode). A program in the user ROM area is executed after a hardware reset occurs while an "L" signal is applied to the CNVSS pin. However, the boot ROM area cannot be read.
00F000h 00FFFFh
Block A : 4 Kbytes (4)
0F0000h
0D0000h Block 7 : 64 Kbytes
Block 5 : 32 Kbytes
0DFFFFh 0E0000h ROM Capacity 192 Kbytes ROM Capacity 128 Kbytes 0E7FFFh 0E8000h 0EFFFFh ROM Capacity 96 Kbytes 0F0000h Block 0-5 (32+8+8+8+4+4) Kbytes 0FFFFFh User ROM area NOTES: Block 6 : 64 Kbytes
0F7FFFh 0F8000h Block 4 : 8 Kbytes 0F9FFFh 0FA000h Block 3 : 8 Kbytes 0FBFFFh 0FC000h Block 2 : 8 Kbytes 0FDFFFh 0FE000h 0FEFFFh 0FF000h 0FFFFFh Block 1 : 4 Kbytes Block 0 : 4 Kbytes 0FF000h 0FFFFFh 4 Kbytes Boot ROM area
1. The boot ROM area can only be rewritten in parallel input/output mode. 2. To specify a block, use an even address in that block. 3. Shown here is a block diagram during single-chip mode. 4. Block A can be made usable by setting the PM10 bit in the PM1 register to "1" (block A enabled, CS2 area allocated at addresses 10000h to 26FFFh).
Figure 19.1
Flash Memory Block Diagram
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19. Flash Memory Version
19.1.1
Boot Mode
The microcomputer enters boot mode when a hardware reset occurs while an "H" signal is applied to the CNVSS and P5_0 pins and an "L" signal is applied to the P5_5 pin. A program in the boot ROM area is executed. In boot mode, the FMR05 bit in the FMR0 register selects access to the boot ROM area or the user ROM area. The rewrite control program for standard serial I/O mode is stored in the boot ROM area before shipment. The boot ROM area can be rewritten in parallel I/O mode only. If any rewrite control program using erase-write mode (EW0 mode) is written in the boot ROM area, the flash memory can be rewritten according to the system implemented.
19.2
Functions To Prevent Flash Memory from Rewriting
The flash memory has a built-in ROM code protect function for parallel I/O mode and a built-in ID code check function for standard I/O mode to prevent the flash memory from reading or rewriting.
19.2.1
ROM Code Protect Function
The ROM code protect function inhibits the flash memory from being read or rewritten during parallel input/ output mode. Figure 19.2 shows the ROMCP Address. The ROMCP address is located in the user ROM area. The ROM code protect function is enabled when the ROMCR bits are set to other than "11b". In this case, set the bit 5 to bit 0 to "111111b". When exiting ROM code protect, erase the block including the ROMCP address by the CPU rewrite mode or the standard serial I/O mode.
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19. Flash Memory Version
19.2.2
ID Code Check Function
Use the ID code check function in standard serial I/O mode. The ID code sent from the serial programmer is compared with the ID code written in the flash memory for a match. If the ID codes do not match, commands sent from the serial programmer are not accepted. However, if the four bytes of the reset vector are "FFFFFFFFh", ID codes are not compared, allowing all commands to be accepted. The ID codes are 7-byte data stored consecutively, starting with the first byte, into addresses 0FFFDFh, 0FFFE3h, 0FFFEBh, 0FFFEFh, 0FFFF3h, 0FFFF7h, and 0FFFFBh. The flash memory must have a program with the ID codes set in these addresses. Figure 19.3 shows address for ID code stored. Reserved character sequence of the ASCII codes: "A", "L", "e", "R", "A", "S", and "E" are used for forced erase function. Table 19.3 lists reserved character sequence. When the ID codes stored in the ID code addresses in the user ROM area are set to the ASCII codes: "A", "L", "e", "R", "A", "S", and "E" as the combination table listed in Table 19.3, forced erase function becomes active. Use the sequence only when forced erase function is necessary.
Table 19.3
Reserved Character Sequence (Reserved Word)
ID Code Address FFFDFh FFFE3h FFFEBh FFFEFh FFFF3h FFFF7h FFFFBh ID1 ID2 ID3 ID4 ID5 ID6 ID7
lD Code Hexadecimal Code (ASCII) 41h (A) 4Ch (L) 65h (e) 52h (R) 41h (A) 53h (S) 45h (E)
Reserve word for forced erase function: A set of reserved characters that match all the ID code addresses in sequence as the combination table listed in Table 19.3.
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19. Flash Memory Version
19.2.3
Forced Erase Function
This function is available only in standard serial I/O mode. When the reserved characters, "A", "L", "e", "R", "A", "S", and "E" in ASCII code, are sent from the serial programmer as ID codes, the content of the user ROM area will be erased at once. However, if the ID codes stored in the ID code addresses in the user ROM area are set to other than a reserved word "ALeRASE" (other than the combination table listed in Table 19.3) when the ROMCP bit in the ROMCP address is set to other than 11b (ROM code protect enabled), forced erase function is ignored and ID code check is executed. Table 19.4 lists conditions and functions for forced erase function. When both the ID codes sent from the serial programmer and the ID codes stored in the ID code addresses correspond to the reserved word ALeRASE", the user ROM area will be erased. However, when the serial programmer sends other than "ALeRASE", even if the ID codes stored in the ID code addresses are "ALeRASE", there is no ID match and any command is ignored. The user ROM area remains protected accordingly.
Table 19.4
Forced Erase Function
ID code from serial programmer ALeRASE
Condition Code in ID code stored address ALeRASE Other than ALeRASE
Function ROMCP1 bit in the ROMCP address User ROM area all erase (forced erase 11b (ROM code pro- function) tect disabled) 00b, 01b, 10b (ROM ID code check code protect enabled) - ID code check (no ID match) - ID code check
-
Other than ALeRASE
ALeRASE Other than ALeRASE
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19. Flash Memory Version
ROM Code Protect Control Address
b7 b6 b5 b4 b3 b2 b1 b0
(5)
111111
Symbol ROMCP Bit Symbol -- (b5-b0)
Address 0FFFFFh Bit Name Reserved Bit Set to "1"
Factory Setting FFh (4) Function RW RW
ROMCP1
ROM Code Protect Level 1 Set b7 b6 Bit (1, 2, 3, 4) 00: 01: ROM code protection active 10: 1 1 : ROM code protection inactive
RW
NOTES : 1. When the ROM code protection is active by the ROMCP1 bit setting, the flash memory is protected against reading or rew riting in parallel I/O mode. 2. Set the bit 5 to bit 0 to "111111b" w hen the ROMCP1 bit is set to a value other than "11b". If the bit 5 to bit 0 are set to values other than "111111b", the ROM code protection may not become active by setting the ROMCP1 bit to a value other than "11b". 3. To make the ROM code protection inactive, erase a block including the ROMCP address in standard serial I/O mode or CPU rew rite mode. 4. The ROMCP address is set to "FFh" w hen a block, including the ROMCP address, is erased. 5. When a value of the ROMCP address is "00h" or "FFh", the ROM code protect function is disabled.
Figure 19.2
ROMCP Address
Address 0FFFDFh to 0FFFDCh 0FFFE3h to 0FFFE0h 0FFFE7h to 0FFFE4h 0FFFEBh to 0FFFE8h 0FFFEFh to 0FFFECh 0FFFF3h to 0FFFF0h 0FFFF7h to 0FFFF4h 0FFFFBh to 0FFFF8h 0FFFFFh to 0FFFFCh ID3 ID4 ID5 ID6 ID7 ROMCP ID1 ID2
Undefined instruction vector
Overflow vector BRK instruction vector Address match vector Single step vector Watchdog timer vector DBC vector NMI vector Reset vector
4 bytes
Figure 19.3 Address for ID Code Stored
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19. Flash Memory Version
19.3
CPU Rewrite Mode
In CPU rewrite mode, the user ROM area can be rewritten when the CPU executes software commands. The user ROM area can be rewritten with the microcomputer mounted on a board without using a parallel or serial programmer. In CPU rewrite mode, only the user ROM area shown in Figure 19.1 can be rewritten. The boot ROM area cannot be rewritten. Program and the block erase command are executed only in the user ROM area. Erase-write 0 (EW0) mode and erase-write 1 (EW1) mode are provided as CPU rewrite mode. Table 19.5 lists differences between erase-write 0 (EW0) and erase-write 1 (EW1) modes. Table 19.5 EW0 Mode and EW1 Mode Item EW0 Mode Operating Mode * Single-chip mode * Memory expansion mode * Boot mode Space where the * User ROM area rewrite control * Boot ROM area program can be placed Space where the The rewrite control program must be rewrite control transferred to any space other than the program can be flash memory (e.g., RAM) before being executed executed (2) Space which can be User ROM area rewritten
EW1 Mode * Single-chip mode
* User ROM area
The rewrite control program can be executed in the user ROM area
Software Command Restriction
None
Mode after Program Read status register mode or Erasing Operating CPU State during Auto Write and Auto Erase Flash Memory State * Read the FMR00, FMR06 and FMR07 Detection bits in the FMR0 register by program * Execute the read status register command to read the SR7, SR5 and SR4 bits in the status register.
User ROM area However, this excludes blocks with the rewrite control program * Program and block erase commands cannot be executed in a block having the rewrite control program. * Read status register command cannot be used. Read array mode Maintains hold state (I/O ports maintains the state before the command was executed) (1) Read the FMR00, FMR06 and FMR07 bits in the FMR0 register by program
NOTES: 1. Do not generate an interrupt (except NMI interrupt) or DMA transfer. 2. When in CPU mode, the PM10 bit in the PM1 register is set to "1". Execute the rewrite control program in the internal RAM or in an external area usable when the PM10 bit is "1".
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19. Flash Memory Version
19.3.1
EW0 Mode
The microcomputer enters CPU rewrite mode by setting the FMR01 bit in the FMR0 register to "1" (CPU rewrite mode enabled) and is ready to accept commands. EW0 mode is selected by setting the FMR11 bit in the FMR1 register to "0". To set the FMR01 bit to "1", set to "1" after first writing "0". The software commands control programming and erasing. The FMR0 register or the status register indicates whether a program or erase operation is completed as expected or not.
19.3.2
EW1 Mode
EW1 mode is selected by setting the FMR11 bit to "1" after the FMR01 bit is set to "1". (Both bits must be set to "0" first before setting to "1".) The FMR0 register indicates whether or not a program or erase operation has been completed as expected. The status register cannot be read in EW1 mode. When an erase/program operation is initiated the CPU halts all program execution until the operation is completed or erase-suspend is requested.
19.3.3
Flash Memory Control Register (FMR0 and FMR1 registers)
Figure 19.4 to Figure 19.5 show the FMR0 and FMR1 Registers.
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19. Flash Memory Version
Flash Memory Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol FMR0 Bit Symbol
___
Address 01B7h Bit Name RY/BY Status Flag CPU Rew rite Mode Select Bit (1) Lock Bit Disable Select Bit (2) Flash Memory Stop Bit
(3, 5)
After Reset 00000001b Function 0 : Busy (being w ritten or erased) 1 : Ready 0 : Disables CPU rew rite mode 1 : Enables CPU rew rite mode 0 : Enables lock bit 1 : Disables lock bit 0 : Enables flash memory operation 1 : Stops flash memory operation (placed in low pow er mode, flash memory initialized) Set to "0" 0 : Boot ROM area is accessed 1 : User ROM area is accessed 0 : Terminated normally 1 : Terminated in error 0 : Terminated normally 1 : Terminated in error RW RO RW RW
FMR00 FMR01 FMR02
FMSTP
RW
-- (b4) FMR05 FMR06 FMR07
Reserved Bit User ROM Area Select Bit (3) (Effective in Only Boot Mode) Program Status Flag (4) Erase Status Flag (4)
RW RW RO RO
NOTES : 1. To set this bit to "1," w rite "0" and then "1" in succession. Make sure no interrupts or DMA transfers w ill occur before w riting "1" after w ____ "0". riting Write to this bit w hen the NMI pin is in the high state. Also, w hile in EW0 mode, w rite to this bit from a program in than the flash memory. Enter read array mode and set this bit to "0". 2. To set this bit to "1," w rite "0" and then "1" in succession w hen the FMR01 bit = 1. Make sure no interrupts or no DMA transfers w ill occur ____ before w riting "1" after w riting "0". Write to this bit w hen the NMI pin is in the high state. 3. Write to this bit from a program in other than the flash memory. 4. This flag is cleared to "0" by executing the Clear Status command. 5. Effective w hen the FMR01 bit = 1 (CPU rew rite mode). If the FMR01 bit = 0, although the FMR03 bit can be set to "1" by w riting "1" in a program, the flash memory is neither placed in low pow er mode nor initialized. 6. This status includes w riting or reading w ith the Lock Bit Program or Read Lock Bit Status command.
Figure 19.4
FMR0 Register
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19. Flash Memory Version
Flash Memory Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
00
0
Symbol FMR1 Bit Symbol -- (b0) FMR11 -- (b3-b2) -- (b5-b4) FMR16 -- (b7)
Address 01B5h Bit Name Reserved Bit EW1 Mode Select Bit (1) Reserved Bit Reserved Bit Lock Bit Status Flag Reserved Bit
After Reset 0X00XX0Xb Function The value in this bit w hen read is indeterminate 0: EW0 mode 1: EW1 mode The value in this bit w hen read is indeterminate Set to "0" 0: Lock 1: Unlock Set to "0" RW RO RW RO RW RO RW
NOTES : 1. To set this bit to "1," w rite "0" and then "1" in succession w hen the FMR01 bit = 1. Make sure no interrupts or DMA transfers w ill occur before w riting "1" after w riting "0". ____ Write to this bit w hen the NMI pin is in the high state. The FMR01 and FMR11 bits both are cleared to "0" by setting the FMR01 bit to "0".
Figure 19.5
FMR1 Register
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19.3.3.1
FMR00 Bit
This bit indicates the flash memory operating state. It is set to "0" while the program, block erase, lock bit program, or read lock bit status command is being executed; otherwise, it is set to "1".
19.3.3.2
FMR01 Bit
The microcomputer can accept commands when the FMR01 bit is set to "1" (CPU rewrite mode). Set the FMR05 bit to "1" (user ROM area access) as well if in boot mode.
19.3.3.3
FMR02 Bit
The lock bit is disabled by setting the FMR02 bit to "1" (lock bit disabled). (Refer to 19.3.6 Data Protect Function.) The lock bit is enabled by setting the FMR02 bit to "0" (lock bit enabled). The FMR02 bit does not change the lock bit status but disables the lock bit function. If the block erase command is executed when the FMR02 bit is set to "1", the lock bit status changes "0" (locked) to "1" (unlocked) after command execution is completed.
19.3.3.4
FMSTP Bit
The FMSTP bit resets the flash memory control circuits and minimizes power consumption in the flash memory. Access to the flash memory is disabled when the FMSTP bit is set to "1". Set the FMSTP bit by program in a space other than the flash memory. * Set the FMSTP bit to "1" if one of the followings occurs: A flash memory access error occurs while erasing or programming in EW0 mode (FMR00 bit does not switch back to "1" (ready)). * Low-power consumption mode is entered Use the following procedure to change the FMSTP bit setting. To stop the flash memory, (1) Set the FMSTP bit to "1" (2) Set tps (the wait time to stabilize flash memory circuit) To restart the flash memory, (1) Set the FMSTP bit to "0" (2) Set tps (the wait time to stabilize flash memory circuit) Figure 19.8 shows a Flow Chart Illustrating How To Start and Stop the Flash Memory Processing Before and After Low Power Dissipation Mode. Follow the procedure on this flow chart. When entering stop or wait mode, the flash memory is automatically turned off. When exiting stop or wait mode, the flash memory is turned back on. The FMR0 register does not need to be set.
19.3.3.5
FMR05 Bit
This bit selects the boot ROM or user ROM area in boot mode. Set to "0" to access (read) the boot ROM area or to "1" (user ROM access) to access (read, write or erase) the user ROM area.
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19.3.3.6
FMR06 Bit
This is a read-only bit indicating an auto program operation state. The FMR06 bit is set to "1" when a program error occurs; otherwise, it is set to "0". Refer to 19.3.8 Full Status Check.
19.3.3.7
FMR07 Bit
This is a read-only bit indicating the auto erase operation status. The FMR07 bit is set to "1" when an erase error occurs; otherwise, it is set to "0". For details, refer to 19.3.8 Full Status Check.
19.3.3.8
FMR11 Bit
EW0 mode is entered by setting the FMR11 bit to "0" (EW0 mode). EW1 mode is entered by setting the FMR11 bit to "1" (EW1 mode).
19.3.3.9
FMR16 Bit
This is a read-only bit indicating the execution result of the read lock bit status command. When the block, where the read lock bit status command is executed, is locked, the FMR16 bit is set to "0". When the block, where the read lock bit status command is executed, is unlocked, the FMR16 bit is set to "1".
Figure 19.6 shows Setting and Resetting of EW0 Mode. Figure 19.7 show Setting and Resetting of EW1 Mode.
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Procedure to Enter EW0 Mode
Rewrite control program Single-chip mode, memory expansion mode or boot mode In boot mode only Set the FMR05 bit to "1" (user ROM area accessed)
Transfer the rewrite control program in CPU rewrite mode to a space other than the flash memory (5)
Set the FMR01 bit to "1" (CPU rewrite mode enabled) after writing "0" (2)
Execute the software commands Set CM0, CM1 and PM1 registers (1)
Execute the read array command (3) Jump to the rewrite control program transferred to a space other than the flash memory. (In the following steps, use the rewrite control program in a space other than the flash memory)
Set the FMR01 bit to "0" (CPU rewrite mode disabled)
In boot mode only Set the FMR05 bit to "0" (boot ROM area accessed) (4)
Jump to a desired address in the flash memory
NOTES : 1. In CPU rewrite mode, set the CM06 bit in the CM0 register and CM17 to 6 bits in the CM1 register to CPU clock frequency of 10.0 MHz or less. Set the PM17 bit in the PM1 register to "1" (with wait state). 2. Set the FMR01 bit to "1" immmediately after setting it to "0" Do not generate an interrupt or a DMA transfer between setting the bit to "0" and setting it to "1". Set the bit to "0". Set this in a space other than flash memory while the NMI pin is held "H". 3. Exit CPU rewrite mode after executing the read array command. 4. When CPU rewrite mode is exited while FMR05 bit is set to "1", the user ROM area can be accessed. 5. When in CPU mode, the PM10 bit in the PM1 register is set to "1". Execute the rewrite control program in the internal RAM or in an external area usable when the PM10 bit is "1".
Figure 19.6
Setting and Resetting of EW0 Mode
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Procedure to Enter EW1 Mode Program in the ROM
Single-chip mode (1)
Set the CM0, CM1, PM1 registers
(2)
Set the FMR01 bit to "1" (CPU rewrite mode enabled) after writing "0" Set the FMR11 bit to "1" (EW1 mode) after writing "0" (EW1 mode) (3)
Execute the software commands
Set the FMR01 bit to 0 (CPU rewrite mode disabled)
NOTES: 1. In EW1 mode, do not enter memory expansion or boot mode. 2. In CPU rewrite mode, set the CM06 bit in the CM0 register and the CM17 to 6 bits in the CM1 register to CPU clock frequency of 10.0 MHz or less. Set the PM17 bit in the PM1 register to "1" (with wait state). 3. Set the FMR01 bit to "1" immediately after setting it to "0". Do not generate an interrupt or a DMA transfer between setting the bit to "0" and setting it to "1". Set the FMR11 bit to "1" immediately after setting it to "0" while the FMR01 bit is set to "1". Do not generate an interrupt or a DMA transfer between setting the FMR11 bit to 0 and setting it to "1". Set the FMR01 and FMR11 bits while "H" is applied to the NMI pin.
Figure 19.7
Setting and Resetting of EW1 Mode
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Low-power consumption mode program Transfer the low-power consumption mode program to a space other than the one time flash memory Set the FMR01 bit to "1" after setting it to "0" (FMSTP bit enabled)
Jump to the low-power consumption mode program transferred to a space other than the one time flash memory. (In the following steps, use the program in a space other than the one time flash memory.)
Set the FMSTP bit to "1" (The one time flash memory stops operating. It is in a low-power consumption state) (1)
Switch clock source of the CPU clock. The main clock stops.(2)
Process in low-power consumption mode.(4)
Start main clock oscillation
Wait until oscillation stabilizes
Switch clock source of the CPU clock (2)
NOTES: 1. Set the FMSTP bit to "1" after the FMR01 bit is set to "1" (FMSTP bit disabled). 2. Wait until clock stabilizes to switch clock source of the CPU clock to the main clock or sub clock. 3. Add tps wait time by program. Do not access the one time flash memory during this wait time. 4. Before entering wait mode or stop mode, be sure to set the FMR01 bit to "0".
Set the FMSTP bit to "0" (one time flash memory operation)
Set the FMR01 bit to "0" (FMSTP bit disabled)
Wait until the one time flash memory stabilizes (tps) (3)
Jump to a desired address in the the one time flash memory
Figure 19.8
Processing Before and After Low Power Dissipation Mode
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19.3.4
Precautions on CPU Rewrite Mode Operating Speed
19.3.4.1
Set the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register to a CPU clock frequency of 10 MHz or less before entering CPU rewrite mode (EW0 or EW1 mode). Also, set the PM17 bit in the PM1 register to "1" (wait state).
19.3.4.2
Prohibited Instructions
The following instructions cannot be used in EW0 mode because the CPU tries to read data in the flash memory: the UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction.
19.3.4.3
area.
Interrupts (EW0 mode)
* To use interrupts having vectors in a relocatable vector table, the vectors must be relocated to the RAM * The NMI and watchdog timer interrupts are available since the FMR0 and FMR1 registers are forcibly reset
when either interrupt occurs. Allocate the jump addresses for each interrupt service routines to the fixed vector table. Flash memory rewrite operation is suspended when the NMI or watchdog timer interrupt occurs. Execute the rewrite program again after exiting the interrupt routine. * The address match interrupt is not available since the CPU tries to read data in the flash memory.
19.3.4.4
Interrupts (EW1 mode)
* Do not acknowledge any interrupts with vectors in the relocatable vector table or address match interrupt
during the auto program or auto erase period. * Do not use the watchdog timer interrupt. * The NMI interrupt is available since the FMR0 and FMR1 registers are forcibly reset when the interrupt occurs. Allocate the jump address for the interrupt service routine to the fixed vector table. Flash memory rewrite operation is suspended when the NMI interrupt occurs. Execute the rewrite program again after exiting the interrupt service routine.
19.3.4.5
How to Access
To set the FMR01, FMR02 or FMR11 bit to "1", write "1" after first setting the bit to "0". Do not generate an interrupt or a DMA transfer between the instruction to set the bit to "0" and the instruction to set the bit to "1". Set the bit while an "H" signal is applied to the NMI pin.
19.3.4.6
Rewriting in the User ROM Area (EW0 mode)
If the supply voltage drops while rewriting the block where the rewrite control program is stored, the flash memory cannot be rewritten because the rewrite control program is not correctly rewritten. If this error occurs, rewrite the user ROM area while in standard serial I/O mode or parallel I/O mode.
19.3.4.7
Rewriting in the User ROM Area (EW1 mode)
Avoid rewriting any block in which the rewrite control program is stored.
19.3.4.8
DMA Transfer
In EW1 mode, do not perform a DMA transfer while the FMR00 bit in the FMR0 register is set to "0" (auto programming or auto erasing).
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19.3.4.9
Writing Command and Data
Write commands and data to even addresses in the user ROM area.
19.3.4.10 Wait Mode
When entering wait mode, set the FMR01 bit to "0" (CPU rewrite mode disabled) before executing the WAIT instruction.
19.3.4.11 Stop Mode
When entering stop mode, the following settings are required: * Set the FMR01 bit to "0" (CPU rewrite mode disabled). Disable DMA transfer before setting the CM10 bit to "1" (stop mode).
19.3.4.12 Low-Power Consumption Mode
If the CM05 bit is set to "1" (main clock stopped), do not execute the following commands: * Program * Block erase * Lock bit program * Read lock bit status
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19.3.5
Software Commands
Software commands are described below. The command code and data must be read and written in 16-bit units, to and from even addresses in the user ROM area. When writing command code, the 8 high-order bits (D15 to D8) are ignored. Table 19.6 Software Commands
First Bus Cycle Command Read Array Read Status Register Clear Status Register Program Block Erase Lock Bit Program Read Lock Bit Status Mode Write Write Write Write Write Write Write Address X X X WA X BA X Data (D15 to D0) xxFFh xx70h xx50h xx40h xx20h xx77h xx71h Mode Read Write Write Write Write
Second Bus Cycle Address X WA BA BA BA Data (D15 to D0) SRD WD xxD0h xxD0h xxD0h
SRD: Data in the SRD register (D7 to D0) WA: Address to be written (The address specified in the first bus cycle is the same even address as the address specified in the second bus cycle.) WD: 16-bit write data BA: Highest-order block address (must be an even address) X: Any even address in the user ROM space xx: 8 high-order bits of command code (ignored)
19.3.5.1
Read Array Command (FFh)
The read array command reads the flash memory. By writing command code "xxFFh" in the first bus cycle, read array mode is entered. Content of a specified address can be read in 16-bit units after the next bus cycle. The microcomputer remains in read array mode until another command is written. Therefore, contents from multiple addresses can be read consecutively.
19.3.5.2
Read Status Register Command (70h)
The read status register command reads the status register (refer to 19.3.7 Status Register for detail). By writing command code "xx70h" in the first bus cycle, the status register can be read in the second bus cycle. Read an even address in the user ROM area. Do not execute this command in EW1 mode.
19.3.5.3
Clear Status Register Command (50h)
The clear status register command clears the status register. By writing "xx50h" in the first bus cycle, the FMR07 to FMR06 bits in the FMR0 register are set to "00b" and the SR5 to SR4 bits in the status register are set to "00b".
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19.3.5.4
Program Command (40h)
The program command writes 2-byte data to the flash memory. By writing "xx40h" in the first bus cycle and data to the write address in the second bus cycle, an auto program operation (data program and verify) will start. The address value specified in the first bus cycle must be the same even address as the write address specified in the second bus cycle. The FMR00 bit in the FMR0 register indicates whether an auto program operation has been completed. The FMR00 bit is set to "0" (busy) during auto program and to "1" (ready) when an auto program operation is completed. After the completion of an auto program operation, the FMR06 bit in the FMR0 register indicates whether or not the auto program operation has been completed as expected. (Refer to 19.3.8 Full Status Check.) An address that is already written cannot be altered or rewritten. Figure 19.9 shows a Flow Chart of the Program Command Programming. The lock bit protects each block from being programmed inadvertently. (Refer to 19.3.6 Data Protect Function.) In EW1 mode, do not execute this command on the block where the rewrite control program is allocated. In EW0 mode, the microcomputer enters read status register mode as soon as an auto program operation starts. The status register can be read. The SR7 bit in the status register is set to "0" at the same time an auto program operation starts. It is set to "1" when auto program operation is completed. The microcomputer remains in read status register mode until the read array command is written. After completion of an auto program operation, the status register indicates whether or not the auto program operation has been completed as expected.
Start Write the command code "xx40h" to an address to be written Write data to an address to be written
FMR00=1? YES Full status check
NO
Program operation is completed NOTES: 1. Write the command code and data to even addresses.
Figure 19.9
Program Command
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19.3.5.5
Block Erase Command
The block erase command erases each block. By writing "xx20h" in the first bus cycle and "xxD0h" to the highest-order even address of a block in the second bus cycle, an auto erase operation (erase and verify) will start in the specified block. The FMR00 bit in the FMR0 register indicates whether an auto erase operation has been completed. The FMR00 bit is set to "0" (busy) during auto erase and to "1" (ready) when the auto erase operation is completed. After the completion of an auto erase operation, the FMR07 bit in the FMR0 register indicates whether or not the auto erase operation has been completed as expected. (Refer to 19.3.8 Full Status Check.) Figure 19.10 shows a Flow Chart of the Block Erase Command Programming. The lock bit protects each block from being programmed inadvertently. (Refer to 19.3.6 Data Protect Function.) In EW1 mode, do not execute this command on the block where the rewrite control program is allocated. In EW0 mode, the microcomputer enters read status register mode as soon as an auto erase operation starts. The status register can be read. The SR7 bit in the status register is set to "0" at the same time an auto erase operation starts. It is set to "1" when an auto erase operation is completed. The microcomputer remains in read status register mode until the read array command or read lock bit status command is written. Also execute the clear status register command and block erase command at least 3 times until an erase error is not generated when an erase error is generated.
Start Write the command code "xx20h" (1) Write "xxD0h" to the highest-order block address
FMR00=1? YES
NO
Full status check (2, 3)
Block erase operation is completed NOTES: 1. Write the command code and data to even addresses. 2. Refer to "Figure 19.13 Full Status Check and Handling Procedure for Each Error". 3. Execute the clear status register command and block erase command at least 3 times until an erase error is not generated when an erase error is generated.
Figure 19.10 Block Erase Command
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19.3.5.6
Lock Bit Program Command
The lock bit program command sets the lock bit for a specified block to "0" (locked). By writing "xx77h" in the first bus cycle and "xxD0h" to the highest-order even address of a block in the second bus cycle, the lock bit for the specified block is set to "0". The address value specified in the first bus cycle must be the same highest-order even address of a block specified in the second bus cycle. Figure 19.11 shows a Flow Chart of the Lock Bit Program Command Programming. Execute read lock bit status command to read lock bit state (lock bit data). The FMR00 bit in the FMR0 register indicates whether a lock bit program operation is completed. Refer to 19.3.6 Data Protect Function for details on lock bit functions and how to set it to "1" (unlocked).
Start Write the command code "xx77h" to the highest-order block address Write "xxD0h" to the highest-order block address
NO FMR00=1? YES Full status check
Lock bit program operation is completed NOTES: 1. Write the command code and data to even addresses.
Figure 19.11 Lock Bit Program Command
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19.3.5.7
Read Lock Bit Status Command (71h)
The read lock bit status command reads the lock bit state of a specified block. By writing "xx71h" in the first bus cycle and "xxD0h" to the highest-order even address of a block in the second bus cycle, the FMR16 bit in the FMR1 register stores information on whether or not the lock bit of a specified block is locked. Read the FMR16 bit after the FMR00 bit in the FMR0 register is set to "1" (ready). Figure 19.12 shows a Flow Chart of the Read Lock Bit Status Command Programming.
Start
Write the command code "xx71h" Write "xxD0h" to the highest-order block address
NO FMR00=1? YES FMR16=0? YES Block is locked Block is not locked NO
NOTES: 1. Write the command code and data to even addresses.
Figure 19.12 Read Lock Bit Status Command
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19.3.6
Data Protect Function
Each block in the flash memory has a nonvolatile lock bit. The lock bit is enabled by setting the FMR02 bit to "0" (lock bit enabled). The lock bit allows each block to be individually protected (locked) against program and erase. This helps prevent data from being inadvertently written to or erased from the flash memory. * When the lock bit status is set to "0", the block is locked (block is protected against program and erase). * When the lock bit status is set to "1", the block is not locked (block can be programmed or erased). The lock bit status is set to "0" (locked) by executing the lock bit program command and to "1" (unlocked) by erasing the block. The lock bit status cannot be set to "1" by any commands. The lock bit status can be read by the read lock bit status command. The lock bit function is disabled by setting the FMR02 bit to "1". All blocks are unlocked. However, individual lock bit status remains unchanged. The lock bit function is enabled by setting the FMR02 bit to "0". Lock bit status is retained. If the block erase command is executed while the FMR02 bit is set to "1", the target block is erased regardless of lock bit status. The lock bit status of each block are set to "1" after an erase operation is completed. Refer to 19.3.5 Software Commands for details on each command.
19.3.7
Status Register
The status register indicates the flash memory operation state and whether or not an erase or program operation is completed as expected. The FMR00, FMR06 and FMR07 bits in the FMR0 register indicate status register states. Table 19.7 shows the Status Register. In EW0 mode, the status register can be read when the followings occur. * Any even address in the user ROM area is read after writing the read status register command. * Any even address in the user ROM area is read from when the program, block erase, or lock bit program command is executed until when the read array command is executed.
19.3.7.1
Sequence Status (SR7 and FMR00 Bits)
The sequence status indicates the flash memory operation state. It is set to "0" while the program, block erase, lock bit program, or read lock bit status command is being executed; otherwise, it is set to "1".
19.3.7.2
Erase Status (SR5 and FMR07 Bits)
Refer to 19.3.8 Full Status Check.
19.3.7.3
Program Status (SR4 and FMR06 Bits)
Refer to 19.3.8 Full Status Check.
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Table 19.7 Status Register Bits in Status Bit in FMR0 Definition Value after Status name Register Register "0" "1" Reset - Reserved - - - SR0 (D0) SR1 (D1) - Reserved - - - SR2 (D2) - Reserved - - - SR3 (D3) - Reserved - - - SR4 (D4) FMR06 Program status Terminated normally Terminated in error 0 SR5 (D5) FMR07 Erase status Terminated normally Terminated in error 0 - Reserved - - - SR6 (D6) SR7 (D7) FMR00 Sequencer status Busy Ready 1
* D0 to D7: These data buses are read when the read status register command is executed. * The FMR07 bit (SR5) and FMR06 bit (SR4) are set to "0" by executing the clear status register command. * When the FMR07 bit (SR5) or FMR06 bit (SR4) is set to "1," the program, block erase, and lock bit program commands are not accepted.
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19.3.8
Full Status Check
If an error occurs when a program or erase operation is completed, the FMR06 to FMR07 bits in the FMR0 register are set to "1", indicating a specific error. Therefore, execution results can be confirmed by checking these bits (full status check). Table 19.8 lists Errors and FMR0 Register State. Figure 19.13 shows a flow chart of the Full Status Check and Handling Procedure for Each Error. Table 19.8 Errors and FMR0 Register State FMR0 Register (Status Register) State Error Error Occurrence Conditions FMR07 bit FMR06 bit (SR5 bit) (SR4 bit) Command * Command is written incorrectly Sequence error * A value other than "xxD0h" or "xxFFh" is written in the 1 1 second bus cycle of the lock bit program or block erase command (1) Erase error * The block erase command is executed on a locked block * The block erase command is executed on an unlock 1 0 block and auto erase operation is not completed as expected (2) Program error * The program command is executed on locked blocks * The program command is executed on unlocked blocks but program operation is not completed as expected 0 1 * The lock bit program command is executed but program operation is not completed as expected (2)
NOTES: 1. The flash memory enters read array mode by writing command code "xxFFh" in the second bus cycle of these commands. The command code written in the first bus cycle becomes invalid. 2. When the FMR02 bit is set to "1" (lock bit disabled), no error occurs even under the conditions above.
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Full status check
FMR06 =1 and FMR07=1?
YES Command sequence error
(1) Execute the clear status register command and set the SR4 and SR5 bits to "0" (completed as expected) . (2) Rewrite command and execute again.
NO NO FMR07=0? Erase error
(1) Execute the clear status register command and set the SR5 bit to "0". (2) Execute the lock bit read status command. Set the FMR02 bit to "1" (lock bit disabled) if the lock bit in the block where the error occurred is set to "0" (locked). (3) Execute the block erase command again. (4) Execute (1), (2) and (3) at least 3 times until an erase error is not generated. NOTE: If similar error occurs, that block cannot be used. If the lock bit is set to "1" (unlocked) in (2) above, that block cannot be used.
YES
NO FMR06=0? Program error
[When a program operation is executed] (1) Execute the clear status register command and set the SR4 bit to "0" (completed as expected) . (2) Execute the read lock bit status command and set the FMR02 bit to "1" if the lock bit in the block where the error occurred is set to 0. (3) Execute the program command again. NOTE: When a similar error occurs, that block cannot be used. If the lock bit is set to "1" in (2) above, that block cannot be used.
YES
[When a lock bit program operation is executed] (1) Execute the clear status register command and set the SR4 bit to "0". (2) Set the FMR02 bit in the FMR0 register to "1". (3) Execute the block erase command to erase the block where the error occurred. (4) Execute the lock bit program command again. NOTE: If similar error occurs, that block cannot be used.
Full status checkcompleted
NOTE: When either FMR06 or FMR07 bit is set to "1" (terminated by error) , the program, block erase, lock bit program and read lock bit status commands cannot be accepted. Execute the clear status register command before each command.
Figure 19.13
Full Status Check and Handling Procedure for Each Error
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19.4
Standard Serial I/O Mode
In standard serial I/O mode, the serial programmer supporting the M16C/30P Group can be used to rewrite the flash memory user ROM area in the microcomputer mounted on a board. For more information about the serial programmer, contact your serial programmer manufacturer. Refer to the user's manual included with your serial programmer for instructions. Table 19.9 lists Pin Functions (Flash Memory Standard Serial I/O Mode). Figure 19.14 to Figure 19.15 show Pin Connections in Serial I/O Mode.
19.4.1
ID Code Check Function
The ID code check function determines whether the ID codes sent from the serial programmer matches those written in the flash memory. (Refer to 19.2 Functions To Prevent Flash Memory from Rewriting.)
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Table 19.9
Pin VCC1, VCC2, VSS CNVSS RESET XIN XOUT BYTE AVCC, AVSS VREF P0_0 to P0_7 P1_0 to P1_7 P2_0 to P2_7 P3_0 to P3_7 P4_0 to P4_7 P5_1 to P5_4, P5_6, P5_7 P5_0 P5_5 P6_0 to P6_3 P6_4/RTS1
Pin Functions (Flash Memory Standard Serial I/O Mode)
Name Power Input CNVSS Reset Input Clock Input Clock Output BYTE Analog Power Supply Input Reference Voltage Input Input Port P0 Input Port P1 Input Port P2 Input Port P3 Input Port P4 Input Port P5 CE Input EPM Input Input Port P6 BUSY Output I/O Description Apply the Flash Program, Erase Voltage to VCC1 pin and VCC2 pin. Apply 0 V to VSS pin. Connect to VCC1 pin. Reset input pin. While RESET pin is "L" level, input a 20 cycle or longer clock to XIN pin. Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins. To input an externally generated clock, input it to XIN pin and open XOUT pin. Connect this pin to VCC1 or VSS. Connect AVSS to VSS and AVCC to VCC1, respectively. Enter the reference voltage for A/D from this pin. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" level signal. Input "L" level signal. Input "H" or "L" level signal or open. Standard serial I/O mode 1: BUSY signal output pin Standard serial I/O mode 2: Monitors the boot program operation check signal output pin. Standard serial I/O mode 1: Serial clock input pin Standard serial I/O mode 2: Input "L". Serial data input pin. Serial data output pin. (1) Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "L" level signal. (2) Connect this pin to VCC1. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open.
I I I O I I I I I I I I I I I O
P6_5/CLK1 P6_6/RXD1 P6_7/TXD1 P7_0 to P7_7 P8_0 to P8_3, P8_6, P8_7 P8_4 P8_5/NMI P9_0 to P9_7 P10_0 to P10_7
SCLK Input RXD Input TXD Input Input Port P7 Input Port P8 P8_4 input NMI Input Input Port P9 Input Port P10
I I O I I I I I I
NOTES: 1. When using the standard serial I/O mode, the internal pull-up is enabled for the TXD1 (P6_7) pin while the RESET pin is "L". 2. When using the standard serial I/O mode, the P0_0 to P0_7, P1_0 to P1_7 pins may become indeterminate while the P8_4 pin is "H" and the RESET pin is "L". If this causes a program, apply "L" to the P8_4 pin.
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19. Flash Memory Version
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 50 49 48 47 46 45 44 43
CE
M16C/30P Group Flash Memory Version
42 41 40 39 38 37 36 35 34 33 32 31
EPM
BUSY SCLK RXD TXD
VSS
Mode setup method
Connect oscillator circuit.
RESET
Signal CNVSS EPM RESET CE
Value VCC1 VSS VSS to VCC1 VCC1
Package: PRQP0100JB-A (100P6S-A)
CNVSS VCC1
Figure 19.14
Pin Connections for Serial I/O Mode (1)
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19. Flash Memory Version
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 23 45 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 CE
M16C/30P Group Flash Memory Version
41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 BUSY SCLK RXD TXD EPM
VSS
Mode setup method
Connect oscillator circuit.
RESET
Signal CNVSS EPM RESET CE
Value VCC1 VSS VSS to VCC1 VCC1
CNVSS
Figure 19.15
Pin Connections for Serial I/O Mode (2)
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VCC1
Package: PLQP0100KB-A (100P6Q-A)
M16C/30P Group
19. Flash Memory Version
19.4.2
Example of Circuit Application in the Standard Serial I/O Mode
Figure 19.16 and Figure 19.17 show example of Circuit Application in Standard Serial I/O Mode 1 and Mode 2, respectively. Refer to the user's manual of your serial programmer to handle pins controlled by the serial programmer.
VCC1 VCC1
Microcomputer SCLK input VCC1 TXD output BUSY output RXD input VCC1 P6_7/TXD1 P6_4/RTS1 P6_6/RXD1 CNVSS P6_5/CLK1 P5_0(CE) P5_5(EPM)
VCC1
VCC1 Reset input User reset signal RESET P8_5/NMI
NOTES: 1. Control pins and external circuitry will vary depending on a programmer. For more information, see the programmer manual. 2. In this example, modes are switched between single-chip mode and standard serial input/output mode by controlling the CNVSS input with a switch. 3. If in standard serial input/output mode 1 there is a possibility that the user reset signal will go low during serial input/output mode, break the connection between the user reset signal and RESET pin by using, for example, a jumper switch.
Figure 19.16
Circuit Application in Standard Serial I/O Mode 1
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19. Flash Memory Version
Microcomputer P6_5/CLK1 TXD output Monitor output RXD intput VCC1 P6_7/TXD1 P6_4/RTS1 P6_6/RXD1 CNVSS
VCC1
P5_0(CE) P5_5(EPM) VCC1
VCC1 Reset input User reset signal RESET P8_5/NMI
NOTES: 1. In this example, modes are switched between single-chip mode and standard serial input/output mode by controlling the CNVSS input with a switch.
Figure 19.17
Circuit Application in Standard Serial I/O Mode 2
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M16C/30P Group
19. Flash Memory Version
19.5
Parallel I/O Mode
In parallel I/O mode, the user ROM area and the boot ROM area can be rewritten by a parallel programmer supporting the M16C/30P Group. Contact your parallel programmer manufacturer for more information on the parallel programmer. Refer to the user's manual included with your parallel programmer for instructions.
19.5.1
User ROM and Boot ROM Areas
An erase block operation in the boot ROM area is applied to only one 4 Kbyte block. The rewrite control program in standard serial I/O mode is written in the boot ROM area before shipment. Do not rewrite the boot ROM area if using the serial programmer. In parallel I/O mode, the boot ROM area is located in addresses 0FF000h to 0FFFFFh. Rewrite this address range only if rewriting the boot ROM area. (Do not access addresses other than addresses 0FF000h to 0FFFFFh.)
19.5.2
ROM Code Protect Function
The ROM code protect function prevents the flash memory from being read and rewritten in parallel I/O mode. (Refer to 19.2 Functions To Prevent Flash Memory from Rewriting.)
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20. One Time Flash Version
20. One Time Flash Version
The one time flash version microcomputer has the same functions as the masked ROM version except the built-in flash memory. The flash memory will be referred to as the one time flash memory in the one time flash version chapter. The one time flash memory can be written in standard serial I/O mode. It cannot be erased. Table 20.1 lists One Time Flash Memory Version Specifications. See Table 1.1 Performance Outline of M16C/30P Group for the items not listed in Table 20.1. Table 20.1 One Time Flash Memory Version Specifications Item Specification Program Method In units of word Program Endurance 1 time Data Retention 10 years ROM Code Protection Parallel I/O modes and standard serial I/O modes are supported
Table 20.2 One Time Flash Memory Rewrite Modes Overview Flash Memory Rewrite Standard Serial I/O Mode Parallel I/O Mode Mode The user ROM area is written using a Boot ROM area and user ROM area dedicated serial programmer. are rewritten using a dedicated Standard serial I/O mode 1: parallel programmer. Function Clock synchronous serial I/O Standard serial I/O mode 2: UART ROM Programmer Serial programmer Parallel programmer
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20. One Time Flash Version
20.1
Low Consumption Mode
The one time flash memory version enters the low power consumption mode to reduce the power consumption by stopping the one time flash memory. Figure 20.1 shows the FMR0 Register in One Time Flash Memory and Figure 20.2 shows the processing before and after low power consumption mode. To enter stop mode or wait mode, set the FMR01 bit in the FMR0 register to 0 (FMSTP bit disabled). For models including the PM13 bit, when the FMR01 bit in the FMR0 register is 1 (FMSTP bit enabled), the PM13 bit in the PM1 register automatically becomes 1. Store the program to change the FMSTP bit either in external area that is usable when the PM13 bit is set to 1. When the FMR01 bit is changed to 0 (FMSTP bit disabled), the PM13 bit is set back to the value before the change. However, when the PM13 bit value is changed while the FMR01 bit is 1, the changed value is reflected after the FMR01 bit is set to 0. External area does not change depending on FMR01 bit status for models without the PM13 bit. Refer to Figure 6.2 PM1 Register (1) and Figure 6.3 PM1 Register (2) for availability of the PM13 bit in the PM1 Register.
Flash Memory Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
0000
0
Symbol FMR0 Bit Symbol -- (b1) FMR01 -- (b2)
Address 01B7h Bit Name Reserved Bit FMSTP Enable Bit (1) Reserved Bit One time Flash Memory Stop Bit (2, 3)
After Reset 00000001b Function The value in this bit w hen read is indeterminate 0 : FMSTP bit disabled 1 : FMSTP bit enabled Set to "0" 0 : Enables one time flash memory operation 1 : Stops one time flash memory operation (placed in low pow er mode, flash memory initialized) Set to "0" Set to "0" RW RO RW RW
FMSTP
RW
-- (b5-b4) -- (b7-b6)
Reserved Bit Reserved Bit
RW RO
NOTES : 1. To set this bit to "1," w rite "0" and then "1" in succession. Make sure no interrupts or DMA transfers w ill occur before w riting "1" after w ____ "0". riting Write to this bit w hen the NMI pin is in the high state. 2. Set this bit in a program area other than the one time flash memory area. 3. Effective w hen the FMR01 bit = 1 (FMSTP bit enabled). If the FMR01 bit = 0, although the FMSTP bit can be set to "1" by w riting "1" by program, the one time flash memory is neither placed in low pow er mode nor initialized.
Figure 20.1
FMR0 Register in One Time Flash Version
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20. One Time Flash Version
Low-power consumption mode program Transfer the low-power consumption mode program to a space other than the one time flash memory Set the FMR01 bit to "1" after setting it to "0" (FMSTP bit enabled)
Jump to the low-power consumption mode program transferred to a space other than the one time flash memory. (In the following steps, use the program in a space other than the one time flash memory.)
Set the FMSTP bit to "1" (The one time flash memory stops operating. It is in a low-power consumption state) (1)
Switch clock source of the CPU clock. The main clock stops.(2)
Process in low-power consumption mode.(4)
Start main clock oscillation
Wait until oscillation stabilizes
Switch clock source of the CPU clock (2)
NOTES: 1. Set the FMSTP bit to "1" after the FMR01 bit is set to "1" (FMSTP bit disabled). 2. Wait until clock stabilizes to switch clock source of the CPU clock to the main clock or sub clock. 3. Add tps wait time by program. Do not access the one time flash memory during this wait time. 4. Before entering wait mode or stop mode, be sure to set the FMR01 bit to "0".
Set the FMSTP bit to "0" (one time flash memory operation)
Set the FMR01 bit to "0" (FMSTP bit disabled)
Wait until the one time flash memory stabilizes (tps) (3)
Jump to a desired address in the the one time flash memory
Figure 20.2
Processing Before and After Low Power Consumption Mode
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20. One Time Flash Version
20.2
Functions to Prevent One Time Flash Version from Being Read
Parallel I/O mode of one time flash has a ROM code protect function, and Standard I/O mode of one time flash has an ID code check function.
20.2.1
ROM Code Protect Function
The ROM code protect function prevents the one time flash being read in parallel I/O mode. The ROM code protect function is enabled when the address 0FFFFFh is set to "3Fh". The ROM code protect function is disabled when the address 0FFFFFh is set to "00h" or "FFh". Write a program with "3Fh", "00h" or "FFh" set in the address to one time flash version. Table 20.3 lists the values and functions of the address 0FFFFFh. Table 20.3 The Values and Functions of Address 0FFFFFh
Set Value 3Fh 00h FFh Other than the above
Function ROM code protect enabled ROM code protect disabled Do not set.
20.2.2
ID Code Check Function
The ID code check function is used in standard serial I/O mode. The ID code sent from the serial programmer and the ID code written in the one time flash memory are checked to see if they match. If these ID codes do not match, the commands sent from the serial programmer are not acknowledged. However, if the four bytes of the reset vector are FFFFFFFFh, the ID code is not checked and all commands can be acknowledged. The ID codes is 7-byte data stored consecutively, beginning with the first byte, into addresses 0FFFDFh, 0FFFE3h, 0FFFEBh, 0FFFEFh, 0FFFF3h, 0FFFF7h, and 0FFFFBh. Write a programs with the ID codes set at these addresses to the one time flash memory.
Address 0FFFDFh to 0FFFDCh 0FFFE3h to 0FFFE0h 0FFFE7h to 0FFFE4h 0FFFEBh to 0FFFE8h 0FFFEFh to 0FFFECh 0FFFF3h to 0FFFF0h 0FFFF7h to 0FFFF4h 0FFFFBh to 0FFFF8h 0FFFFFh to 0FFFFCh ID3 ID4 ID5 ID6 ID7 "3Fh" (1) ID1 ID2
Undefined instruction vector
Overflow vector BRK instruction vector Address match vector Single step vector Watchdog timer vector DBC vector NMI vector Reset vector
4 bytes
Note1: The ROM code protect function is enabled when it is set to "3Fh".
Figure 20.3 Address for ID Code Stored in One Time Flash Version
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M16C/30P Group
20. One Time Flash Version
20.3
Standard Serial I/O Mode
In standard serial I/O mode, the serial programmer supporting the M16C/30P Group can be used to write (the one time flash memory) user ROM area in the microcomputer mounted on a board. For more information about the serial programmer, contact your serial programmer manufacturer. Refer to the user's manual included with your serial programmer for instructions. Table 20.4 lists Pin Functions (One Time Flash Memory Standard Serial I/O Mode). Figure 20.4 show Pin Connections for Serial I/O Mode.
20.3.1
ID Code Check Function
The ID code check function determines whether the ID codes sent from the serial programmer matches those written in the one time flash memory. (Refer to 20.2 Functions to Prevent One Time Flash Version from Being Read.)
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20. One Time Flash Version
Table 20.4
Pin VCC1, VCC2, VSS CNVSS RESET XIN XOUT BYTE AVCC, AVSS VREF P0_0 to P0_7 P1_0 to P1_7 P2_0 to P2_7 P3_0 to P3_7 P4_0 to P4_7 P5_1 to P5_4, P5_6, P5_7 P5_0 P5_5 P6_0 to P6_3 P6_4/RTS1
Pin Functions (One Time Flash Memory Standard Serial I/O Mode)
Name Power Input CNVSS Reset Input Clock Input Clock Output BYTE Analog Power Supply Input Reference Voltage Input Input Port P0 Input Port P1 Input Port P2 Input Port P3 Input Port P4 Input Port P5 CE Input EPM Input Input Port P6 BUSY Output I/O Description Apply the Flash Program Voltage to VCC1 pin and VCC2 pin. Apply 0 V to VSS pin. Connect to VCC1 pin. Reset input pin. While RESET pin is "L" level, input a 20 cycle or longer clock to XIN pin. Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins. To input an externally generated clock, input it to XIN pin and open XOUT pin. Connect this pin to VCC1 or VSS. Connect AVSS to VSS and AVCC to VCC1, respectively. Enter the reference voltage for A/D from this pin. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" level signal. Input "L" level signal. Input "H" or "L" level signal or open. Standard serial I/O mode 1: BUSY signal output pin Standard serial I/O mode 2: Monitors the boot program operation check signal output pin. Standard serial I/O mode 1: Serial clock input pin Standard serial I/O mode 2: Input "L". Serial data input pin. Serial data output pin. (1) Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "L" level signal. (2) Connect this pin to VCC1. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open.
I I I O I I I I I I I I I I I O
P6_5/CLK1 P6_6/RXD1 P6_7/TXD1 P7_0 to P7_7 P8_0 to P8_3, P8_6, P8_7 P8_4 P8_5/NMI P9_0 to P9_7 P10_0 to P10_7
SCLK Input RXD Input TXD Input Input Port P7 Input Port P8 P8_4 input NMI Input Input Port P9 Input Port P10
I I O I I I I I I
NOTES: 1. When using the standard serial I/O mode, the internal pull-up is enabled for the TXD1 (P6_7) pin while the RESET pin is "L". 2. When using the standard serial I/O mode, the P0_0 to P0_7, P1_0 to P1_7 pins may become indeterminate while the P8_4 pin is "H" and the RESET pin is "L". If this causes a program, apply "L" to the P8_4 pin.
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20. One Time Flash Version
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 12345 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
CE
M16C/30P Group One Time Flash Memory Version Flash Memory Version
M16C/30P Group
EPM
BUSY SCLK RXD TXD
VSS
Mode setup method
Connect oscillator circuit.
RESET
Signal CNVSS EPM RESET CE
Value VCC1 VSS VSS to VCC1 VCC1
Package: PRQP0100JB-A (100P6S-A)
CNVSS VCC1
Figure 20.4
Pin Connections for Serial I/O Mode
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20. One Time Flash Version
20.3.2
Example of Circuit Application in the Standard Serial I/O Mode
Figure 20.5 and Figure 20.6 show example of Circuit Application in Standard Serial I/O Mode 1 and Mode 2, respectively. Refer to the user's manual of your serial programmer to handle pins controlled by the serial programmer.
VCC1 VCC1
Microcomputer SCLK input VCC1 TXD output BUSY output RXD input VCC1 P6_7/TXD1 P6_4/RTS1 P6_6/RXD1 CNVSS P6_5/CLK1 P5_0(CE) P5_5(EPM)
VCC1
VCC1 Reset input User reset signal RESET P8_5/NMI
NOTES: 1. Control pins and external circuitry will vary depending on a programmer. For more information, see the programmer manual. 2. In this example, modes are switched between single-chip mode and standard serial input/output mode by controlling the CNVSS input with a switch. 3. If in standard serial input/output mode 1 there is a possibility that the user reset signal will go low during serial input/output mode, break the connection between the user reset signal and RESET pin by using, for example, a jumper switch.
Figure 20.5
Circuit Application in Standard Serial I/O Mode 1
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20. One Time Flash Version
Microcomputer P6_5/CLK1 TXD output Monitor output RXD intput VCC1 P6_7/TXD1 P6_4/RTS1 P6_6/RXD1 CNVSS
VCC1
P5_0(CE) P5_5(EPM) VCC1
VCC1 Reset input User reset signal RESET P8_5/NMI
NOTES: 1. In this example, modes are switched between single-chip mode and standard serial input/output mode by controlling the CNVSS input with a switch.
Figure 20.6
Circuit Application in Standard Serial I/O Mode 2
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21. Electrical Characteristics
21. Electrical Characteristics
Table 21.1
Symbol VCC AVCC VI
Absolute Maximum Ratings
Parameter Supply Voltage(VCC1=VCC2) Analog Supply Voltage Input Voltage RESET, CNVSS, BYTE, P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, VREF, XIN P7_0, P7_1 Output P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, Voltage P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, XOUT P7_0, P7_1 Power Dissipation Operating When the Microcomputer is Operating Ambient Temperature One Time Flash Program Erase Flash Program Erase Storage Temperature Condition VCC1=VCC2=AVCC VCC1=VCC2=AVCC Rated Value -0.3 to 6.5 -0.3 to 6.5 -0.3 to VCC+0.3 Unit V V V
VO
-0.3 to 6.5 -0.3 to VCC+0.3
V V
Pd Topr
-40C-0.3 to 6.5 300 -20 to 85 / -40 to 85
V mW C
Tstg
0 to 60 0 to 60 -65 to 150
C
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21. Electrical Characteristics
Table 21.2
Symbol VCC AVCC VSS AVSS VIH
Recommended Operating Conditions (1)
Parameter Supply Voltage (VCC1=VCC2) Analog Supply Voltage Supply Voltage Analog Supply Voltage P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7 HIGH Input Voltage P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(during single-chip mode) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (data input during memory expansion and microprocessor mode) P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, XIN, RESET, CNVSS, BYTE P7_0, P7_1
Min. 2.7
Standard Typ. 5.0 VCC 0 0
Max. 5.5
Unit V V V V V V V V V V V V V mA mA mA mA MHz MHz kHz MHz
0.8VCC 0.8VCC 0.5VCC 0.8VCC 0.8VCC 0 0 0 0
VCC VCC VCC VCC 6.5 0.2VCC 0.2VCC 0.16VCC 0.2VCC
-10.0 -5.0
VIL
LOW Input Voltage
P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (during single-chip mode) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (data input during memory expansion and microprocessor mode) P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, XIN, RESET, CNVSS, BYTE
IOH(peak) IOH(avg) IOL(peak) IOL(avg) f(XIN)
HIGH Peak Output Current HIGH Average Output Current LOW Peak Output Current LOW Average Output Current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
10.0 5.0 0 0 32.768 0 16 20xVCC1-44 50 16
f(XCIN) f(BCLK)
Main Clock Input VCC=3.0V to 5.5V Oscillation VCC=2.7V to 3.0V Frequency (4) Sub-Clock Oscillation Frequency CPU Operation Clock
NOTES: 1. Referenced to VCC1 = VCC2 = 2.7 to 5.5V at Topr = -20 to 85C / -40 to 85C unless otherwise specified. 2. The Average Output Current is the mean value within 100ms. 3. The total IOL(peak) for ports P0, P1, P2, P8_6, P8_7, P9 and P10 must be 80mA max. The total IOL(peak) for ports P3, P4, P5, P6, P7 and P8_0 to P8_4 must be 80mA max. The total IOH(peak) for ports P0, P1, and P2 must be -40mA max. The total IOH(peak) for ports P3, P4 and P5 must be -40mA max. The total IOH(peak) for ports P6, P7, and P8_0 to P8_4 must be -40mA max. The total IOH(peak) for ports P8_6, P8_7 and P9 must be -40mA max. Set Average Output Current to 1/2 of peak. 4. Relationship between main clock oscillation frequency, and supply voltage.
Main clock input oscillation frequency
f(XIN) operating maximum frequency [MHz]
20 x VCC1-44MHz
16.0
10.0
0.0 2.7 3.0 5.5
VCC1[V] (main clock: no division)
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21. Electrical Characteristics
Table 21.3
Symbol
- INL
A/D Conversion Characteristics (1)
Parameter Resolution Integral Non-Linearity Error Measuring Condition VREF=VCC VREF= AN0 to AN7 input, AN0_0 to AN0_7 input, VCC= ANEX0, ANEX1 input 5V VREF= AN0 to AN7 input, VCC= AN0_0 to AN0_7 input, 3.3V ANEX0, ANEX1 input VREF=VCC=5V, 3.3V VREF= AN0 to AN7 input, AN0_0 to AN0_7 input, VCC= ANEX0, ANEX1 input 5V VREF= AN0 to AN7 input, AN0_0 to AN0_7 input, VCC =3.3V ANEX0, ANEX1 input VREF=VCC=5V, 3.3V Min. Standard Typ. Max. 10 5 Unit Bits LSB
10bit
7
LSB
-
Absolute Accuracy
8bit 10bit
2 5
LSB LSB
7
LSB
- DNL - - RLADDER tCONV
tCONV tSAMP VREF VIA
8bit Tolerance Level Impedance Differential Non-Linearity Error Offset Error Gain Error Ladder Resistance 10-bit Conversion Time, Sample & Hold Function Available 8-bit Conversion Time, Sample & Hold Function Available Sampling Time Reference Voltage Analog Input Voltage
2 3 2 5 5 40
VREF=VCC VREF=VCC=5V, AD=10MHz VREF=VCC=5V, AD=10MHz
10 3.3 2.8 0.3 3.0 0
LSB k LSB LSB LSB k s
s s V V
VCC VREF
NOTES: 1. Referenced to VCC=AVCC=VREF=3.3 to 5.5V, VSS=AVSS=0V at Topr = -20 to 85C / -40 to 85C unless otherwise specified. 2. AD frequency must be 10 MHz or less. 3. When sample & hold function is disabled, AD frequency must be 250 kHz or more, in addition to the limitation in Note 2. 4. When sample & hold function is enabled, AD frequency must be 1MHz or more, in addition to the limitation in Note 2.
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21. Electrical Characteristics
Table 21.4
Symbol
- - - - - - - tPS -
Flash Memory Version Electrical Characteristics (1)
Parameter Program and Erase Endurance (2) Word Program Time (VCC1=5.0V) Lock Bit Program Time Block Erase Time (VCC1=5.0V) Min. 100(3) Standard Typ. 25 25 0.3 0.3 0.5 0.8 10 Max. 200 200 4 4 4 4 15 Unit cycle s s s s s s s year
4-Kbyte block 8-Kbyte block 32-Kbyte block 64-Kbyte block
Flash Memory Circuit Stabilization Wait Time Data Hold Time (4)
NOTES: 1. Referenced to VCC1=4.5 to 5.5V, 3.0 to 3.6V at Topr = 0 to 60 C (U3, U5) unless otherwise specified. 2. Program and Erase Endurance refers to the number of times a block erase can be performed. If the program and erase endurance is 100, each block can be erased 100 times. For example, if a 4 Kbytes block A is erased after writing 1 word data 2,048 times, each to a different address, this counts as one program and erase endurance. Data cannot be written to the same address more than once without erasing the block. (Rewrite prohibited) 3. Maximum number of E/W cycles for which operation is guaranteed. 4. Topr = -40 to 85 C (U3) / -20 to 85 C (U5).
Table 21.5
Flash Memory Version Program / Erase Voltage and Read Operation Voltage Characteristics
Flash Read Operation Voltage VCC1=2.7 to 5.5 V (Topr = -40C to 85C (U3)
-20C to 85C (U5))
Flash Program, Erase Voltage VCC1 = 3.3 0.3 V or 5.0 0.5 (Topr = 0C to 60C )
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21. Electrical Characteristics
Table 21.6
Symbol
- - tPS -
One Time Flash Version Electrical Characteristics (1)
Parameter Program Endurance Word Program Time (VCC1=5.0V) One Time Flash Memory Circuit Stabilization Wait Time Data Hold Time (4) Min. Standard Typ. 50 10 Max. 1 500 15 Unit cycle s s year
NOTES: 1. Referenced to VCC1=4.5 to 5.5V, 3.0 to 3.6V at Topr = 0 to 60 C (U3, U5) unless otherwise specified. 2. Topr = -40 to 85 C (U3) / -20 to 85 C (U5).
Table 21.7
One Time Flash Version Program Voltage and Read Operation Voltage Characteristics
Flash Read Operation Voltage VCC1=2.7 to 5.5 V (Topr = -40C to 85C (U3)
-20C to 85C (U5))
Flash Program Voltage VCC1 = 3.3 0.3 V or 5.0 0.5 (Topr = 0C to 60C )
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21. Electrical Characteristics
Table 21.8
Symbol td(P-R) td(R-S) td(W-S)
Power Supply Circuit Timing Characteristics
Parameter Time for Internal Power Supply Stabilization During Powering-On STOP Release Time Low Power Dissipation Mode Wait Mode Release Time Measuring Condition VCC=2.7V to 5.5V Min. Standard Typ. Max. 2 1500 1500 Unit ms
s s
td(P-R)
Time for Internal Power Supply Stabilization During Powering-On
Recommended operation voltage VCC CPU clock
td(P-R)
td(R-S)
STOP Release Time
td(W-S)
Low Power Dissipation Mode Wait Mode Release Time
Interrupt for (a) Stop mode release or (b)Wait mode release CPU clock (a) (b)
td(R-S) td(W-S)
Figure 21.1
Power Supply Circuit Timing Diagram
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21. Electrical Characteristics
VCC1=VCC2=5V
Table 21.9
Symbol VOH
HIGH Output Voltage HIGH Output Voltage
Electrical Characteristics(1)
Parameter
(1) Measuring Condition
IOH=-5mA
Min.
Standard Typ.
Max. VCC
Unit
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 XOUT HIGHPOWER LOWPOWER
VCC-2.0
IOH=-200A
V
VOH
VCC-0.3
IOH=-1mA IOH=-0.5mA With no load applied With no load applied IOL=5mA
VCC VCC VCC 2.5 1.6 2.0
V
VOH
HIGH Output Voltage
VCC-2.0 VCC-2.0
V V
HIGH Output Voltage
XCOUT
HIGHPOWER LOWPOWER
VOL
LOW Output Voltage LOW Output Voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 XOUT HIGHPOWER LOWPOWER
V
VOL
IOL=200A
0.45
IOL=1mA IOL=0.5mA With no load applied With no load applied
V
VOL
LOW Output Voltage
2.0 2.0 0 0 0.2 0.2 1.0 2.5
V V
LOW Output Voltage
XCOUT
HIGHPOWER LOWPOWER
VT+-VT-
Hysteresis
TA0IN to TA2IN, TB0IN to TB2IN, INT0 to INT4, NMI, ADTRG, CTS0 to CTS2, CLK0 to CLK2, TA0OUT to TA2OUT, KI0 to KI3, RXD0 to RXD2, SCL0 to SCL2, SDA0 to SDA2 RESET P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, XIN, RESET, CNVSS, BYTE P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, XIN, RESET, CNVSS, BYTE P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 VI=5V
V V
A
VT+-VTIIH
Hysteresis HIGH Input Current
5.0
IIL
LOW Input Current
VI=0V
-5.0
A
RPULLUP Pull-Up
Resistance
VI=0V
30
50 1.5 15
170
k M M V
RfXIN RfXCIN VRAM
Feedback Resistance XIN Feedback Resistance XCIN RAM Retention Voltage At stop mode
2.0
NOTES: 1. Referenced to VCC1=VCC2=4.2 to 5.5V, VSS = 0V at Topr = -20 to 85C / -40 to 85C, f(XIN) =16MHz unless otherwise specified.
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21. Electrical Characteristics
Table 21.10
Symbol ICC
Electrical Characteristics (2) (1)
Parameter Measuring Condition Mask ROM One Time Flash Flash Memory One Time Flash Flash Memory Program Flash Memory Erase Mask ROM One Time Flash
f(XIN)=16MHz No division f(XIN)=16MHz, No division f(XIN)=16MHz, No division f(XIN)=10MHz, VCC1=5.0V f(XIN)=10MHz, VCC1=5.0V f(XIN)=10MHz, VCC1=5.0V f(XCIN)=32kHz Low power dissipation mode, ROM (3) f(XCIN)=32kHz Low power dissipation mode, RAM (3) f(XCIN)=32kHz Low power dissipation mode, Flash Memory (3)
Min.
Standard Typ. Max. 10 10 12 15 15 25 25 25 15 18 18
Unit mA mA mA mA mA mA
A A A A A A A
In single-chip Power Supply Current (VCC1=VCC2=4.0V to 5.5V) mode, the output pins are open and other pins are VSS
350 25 420 7.5 2.0 0.8 3.0
Flash Memory
f(XCIN)=32kHz Low power dissipation mode, RAM (3) f(XCIN)=32kHz Low power dissipation mode, Flash Memory (3)
Mask ROM One Time Flash Flash Memory
f(XCIN)=32kHz Wait mode (2), Oscillation capability High f(XCIN)=32kHz Wait mode (2), Oscillation capability Low Stop mode Topr =25C
A
NOTES: 1. Referenced to VCC1=VCC2=4.2 to 5.5V, VSS = 0V at Topr = -20 to 85C / -40 to 85C, f(XIN)=16MHz unless otherwise specified. 2. With one timer operated using fC32. 3. This indicates the memory in which the program to be executed exists.
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21. Electrical Characteristics
VCC1=VCC2=5V
Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = -20 to 85C / -40 to 85C unless otherwise specified) Table 21.11
Symbol tc tw(H) tw(L) tr tf
External Clock Input (XIN input) (1)
Parameter External Clock Input Cycle Time External Clock Input HIGH Pulse Width External Clock Input LOW Pulse Width External Clock Rise Time External Clock Fall Time Standard Min. 62.5 25 25 Max. Unit ns ns ns ns ns
15 15
NOTES: 1. The condition is VCC1=VCC2=3.0 to 5.0V.
Table 21.12
Symbol tac1(RD-DB) tac2(RD-DB) tsu(DB-RD) tsu(RDY-BCLK) tsu(HOLD-BCLK) th(RD-DB) th(BCLK-RDY) th(BCLK-HOLD)
Memory Expansion Mode and Microprocessor Mode
Parameter Data Input Access Time (for setting with no wait) Data Input Access Time (for setting with wait) Data Input Setup Time RDY Input Setup Time HOLD Input Setup Time Data Input Hold Time RDY Input Hold Time HOLD Input Hold Time Standard Min. Max. (NOTE 1) (NOTE 2) Unit ns ns ns ns ns ns ns ns
40 30 40 0 0 0
NOTES: 1. Calculated according to the BCLK frequency as follows:
9 0.5x10 ----------------------- - 45 [ ns ] f ( BCLK )
2. Calculated according to the BCLK frequency as follows:
9 ( n - 0.5 )x10 ------------------------------------ - 45 [ ns ] f ( BCLK ) n is "2" for 1-wait setting.
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21. Electrical Characteristics
VCC1=VCC2=5V
Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = -20 to 85C / -40 to 85C unless otherwise specified) Table 21.13
Symbol tc(TA) tw(TAH) tw(TAL) TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width
Timer A Input (Counter Input in Event Counter Mode)
Parameter Standard Min. 100 40 40 Max. Unit ns ns ns
Table 21.14
Symbol tc(TA) tw(TAH) tw(TAL)
Timer A Input (Gating Input in Timer Mode)
Parameter TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Standard Min. 400 200 200 Max. Unit ns ns ns
Table 21.15
Symbol tc(TA) tw(TAH) tw(TAL)
Timer A Input (External Trigger Input in One-shot Timer Mode)
Parameter TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Standard Min. 200 100 100 Max. Unit ns ns ns
Table 21.16
Symbol tw(TAH) tw(TAL)
Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Parameter TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Standard Min. 100 100 Max. Unit ns ns
Table 21.17
Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP)
Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)
Parameter TAiOUT Input Cycle Time TAiOUT Input HIGH Pulse Width TAiOUT Input LOW Pulse Width TAiOUT Input Setup Time TAiOUT Input Hold Time Standard Min. 2000 1000 1000 400 400 Max. Unit ns ns ns ns ns
Table 21.18
Symbol tc(TA) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN)
Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Parameter TAiIN Input Cycle Time TAiOUT Input Setup Time TAiIN Input Setup Time Standard Min. 800 200 200 Max. Unit ns ns ns
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21. Electrical Characteristics
VCC1=VCC2=5V
Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = -20 to 85C / -40 to 85C unless otherwise specified) Table 21.19
Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL)
Timer B Input (Counter Input in Event Counter Mode)
Parameter TBiIN Input Cycle Time (counted on one edge) TBiIN Input HIGH Pulse Width (counted on one edge) TBiIN Input LOW Pulse Width (counted on one edge) TBiIN Input Cycle Time (counted on both edges) TBiIN Input HIGH Pulse Width (counted on both edges) TBiIN Input LOW Pulse Width (counted on both edges) Standard Min. 100 40 40 200 80 80 Max. Unit ns ns ns ns ns ns
Table 21.20
Symbol tc(TB) tw(TBH) tw(TBL)
Timer B Input (Pulse Period Measurement Mode)
Parameter TBiIN Input Cycle Time TBiIN Input HIGH Pulse Width TBiIN Input LOW Pulse Width Standard Min. 400 200 200 Max. Unit ns ns ns
Table 21.21
Symbol tc(TB) tw(TBH) tw(TBL)
Timer B Input (Pulse Width Measurement Mode)
Parameter TBiIN Input Cycle Time TBiIN Input HIGH Pulse Width TBiIN Input LOW Pulse Width Standard Min. 400 200 200 Max. Unit ns ns ns
Table 21.22
Symbol tc(AD) tw(ADL)
A/D Trigger Input
Parameter ADTRG Input Cycle Time ADTRG input LOW Pulse Width Standard Min. 1000 125 Max. Unit ns ns
Table 21.23
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D)
Serial Interface
Parameter CLKi Input Cycle Time CLKi Input HIGH Pulse Width CLKi Input LOW Pulse Width TXDi Output Delay Time TXDi Hold Time RXDi Input Setup Time RXDi Input Hold Time Standard Min. 200 100 100 0 70 90 Max. Unit ns ns ns ns ns ns ns
80
Table 21.24
Symbol tw(INH) tw(INL)
External Interrupt INTi Input
Parameter INTi Input HIGH Pulse Width INTi Input LOW Pulse Width Standard Min. 250 250 Max. Unit ns ns
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21. Electrical Characteristics
VCC1=VCC2=5V
Switching Characteristics (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = -20 to 85C / -40 to 85C unless otherwise specified) Table 21.25
Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) td(BCLK-HLDA)
Memory Expansion and Microprocessor Modes (for setting with no wait)
Parameter Address Output Delay Time Address Output Hold Time (in relation to BCLK) Address Output Hold Time (in relation to RD) Address Output Hold Time (in relation to WR) Chip Select Output Delay Time Chip Select Output Hold Time (in relation to BCLK) ALE Signal Output Delay Time ALE Signal Output Hold Time RD Signal Output Delay Time RD Signal Output Hold Time WR Signal Output Delay Time WR Signal Output Hold Time Data Output Delay Time (in relation to BCLK) Data Output Hold Time (in relation to BCLK) (3) Data Output Delay Time (in relation to WR) Data Output Hold Time (in relation to WR) (3) HLDA Output Delay Time Standard Min. Max. 25 -3 0 (NOTE 2) 25 -3 15 -4 25 0 25 0 40 4 (NOTE 1) (NOTE 2) 40 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
See Figure 21.2
NOTES: 1. Calculated according to the BCLK frequency as follows: 9 0.5x10 f(BCLK) is 12.5MHz or less. ----------------------- - 40 [ ns ] f ( BCLK ) 2. Calculated according to the BCLK frequency as follows: 9 0.5x10 ----------------------- - 10 [ ns ] f ( BCLK ) 3. This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = -CR X ln (1-VOL / VCC1) by a circuit of the right figure. For example, when VOL = 0.2VCC1, C = 30pF, R = 1k, hold time of output "L" level is t = -30pF X 1k X In(1-0.2VCC1 / VCC1) = 6.7ns.
R DBi C
P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10
30pF
Figure 21.2
Ports P0 to P10 Measurement Circuit
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21. Electrical Characteristics
VCC1=VCC2=5V
Switching Characteristics (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = -20 to 85C / -40 to 85C unless otherwise specified) Table 21.26 Memory Expansion and Microprocessor Modes (for 1 wait setting and external area access)
Parameter Address Output Delay Time Address Output Hold Time (in relation to BCLK) Address Output Hold Time (in relation to RD) Address Output Hold Time (in relation to WR) Chip Select Output Delay Time Chip Select Output Hold Time (in relation to BCLK) ALE Signal Output Delay Time ALE Signal Output Hold Time RD Signal Output Delay Time RD Signal Output Hold Time WR Signal Output Delay Time WR Signal Output Hold Time Data Output Delay Time (in relation to BCLK) Data Output Hold Time (in relation to BCLK) (3) Data Output Delay Time (in relation to WR) Data Output Hold Time (in relation to WR)(3) HLDA Output Delay Time Standard Min. Max. 25 -3 0 (NOTE 2) 25
-3
Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) td(BCLK-HLDA)
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
15 See Figure 21.2
-4
25 0 25 0 40 4 (NOTE 1) (NOTE 2) 40
NOTES: 1. Calculated according to the BCLK frequency as follows: 9 ( n - 0.5 )x10 ----------------------------------- - 40 [ ns ] n is "1" for 1-wait setting, f(BCLK) is 12.5MHz or less. f ( BCLK ) 2. Calculated according to the BCLK frequency as follows: 9 0.5x10 ----------------------- - 10 [ ns ] f ( BCLK ) 3. This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = -CR X ln (1-VOL / VCC1) by a circuit of the right figure. For example, when VOL = 0.2VCC1, C = 30pF, R = 1k, hold time of output "L" level is t = -30pF X 1k X In(1-0.2VCC1 / VCC1) = 6.7ns.
R DBi C
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21. Electrical Characteristics
VCC1=VCC2=5V
XIN input tr tw(H) tf tc tw(L)
tc(TA) tw(TAH) TAiIN input tw(TAL)
tc(UP) tw(UPH) TAiOUT input tw(UPL)
TAiOUT input (Up/down input) During event counter mode TAiIN input (When count on falling edge is selected) TAiIN input (When count on rising edge is selected) Two-phase pulse input in event counter mode th(TIN-UP) tsu(UP-TIN)
tc(TA)
TAiIN input tsu(TAIN-TAOUT) TAiOUT input tsu(TAOUT-TAIN) tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input tsu(TAIN-TAOUT) tsu(TAOUT-TAIN)
Figure 21.3
Timing Diagram (1)
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21. Electrical Characteristics
VCC1=VCC2=5V
tc(CK) tw(CKH) CLKi tw(CKL) th(C-Q) TXDi td(C-Q) RXDi tw(INL) INTi input tw(INH) tsu(D-C) th(C-D)
Figure 21.4
Timing Diagram (2)
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21. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode, Microprocessor Mode
(Effective for setting with wait)
BCLK
RD (Separate bus) WR, WRL, WRH (Separate bus) RDY input
tsu(RDY-BCLK) th(BCLK-RDY)
(Common to setting with wait and setting without wait)
BCLK
tsu(HOLD-BCLK) th(BCLK-HOLD)
HOLD input
HLDA input P0, P1, P2, P3, P4, P5_0 to P5_2
(1)
td(BCLK-HLDA)
Hi-Z
td(BCLK-HLDA)
NOTES: 1. These pins are set to high-impedance regardless of the input level of the BYTE pin, PM06 bit in PM0 register.
* Measuring conditions : * VCC1=VCC2=5V * Input timing voltage : Determined with VIL=1.0V, VIH=4.0V * Output timing voltage : Determined with VOL=2.5V, VOH=2.5V
Figure 21.5
Timing Diagram (3)
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21. Electrical Characteristics
Memory Expansion Mode, Microprocessor Mode
(For setting with no wait) Read timing
VCC1=VCC2=5V
BCLK td(BCLK-CS)
25ns.max
th(BCLK-CS)
-3ns.min
CSi
tcyc
td(BCLK-AD)
25ns.max
th(BCLK-AD)
-3ns.min
ADi BHE td(BCLK-ALE)
25ns.max
th(BCLK-ALE)
-4ns.min
th(RD-AD)
0ns.min
ALE td(BCLK-RD)
25ns.max
th(BCLK-RD)
0ns.min
RD tac1(RD-DB)
(0.5 x tcyc-45)ns.max Hi-Z
DBi
tsu(DB-RD)
40ns.min
th(RD-DB)
0ns.min
Write timing
BCLK td(BCLK-CS)
25ns.max
th(BCLK-CS)
-3ns.min
CSi
tcyc
td(BCLK-AD)
25ns.max
th(BCLK-AD)
-3ns.min
ADi BHE td(BCLK-ALE)
25ns.max
th(BCLK-ALE)
-4ns.min
(0.5 x tcyc-10)ns.min
th(WR-AD)
ALE td(BCLK-WR)
25ns.max
th(BCLK-WR)
0ns.min
WR, WRL, WRH td(BCLK-DB)
40ns.max Hi-Z
th(BCLK-DB)
4ns.min
DBi td(DB-WR) tcyc= 1 f(BCLK) Measuring conditions * VCC1=VCC2=5V * Input timing voltage : VIL=0.8V, VIH=2.0V * Output timing voltage : VOL=0.4V, VOH=2.4V
(0.5 x tcyc-40)ns.min
(0.5 x tcyc-10)ns.min
th(WR-DB)
Figure 21.6
Timing Diagram (4)
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21. Electrical Characteristics
Memory Expansion Mode, Microprocessor Mode
(for 1-wait setting and external area access) Read timing
BCLK td(BCLK-CS)
25ns.max
VCC1=VCC2=5V
th(BCLK-CS)
-3ns.min
CSi
tcyc
td(BCLK-AD)
25ns.max
th(BCLK-AD)
-3ns.min
ADi BHE td(BCLK-ALE)
25ns.max
th(BCLK-ALE)
-4ns.min
th(RD-AD)
0ns.min
ALE td(BCLK-RD)
25ns.max
th(BCLK-RD)
0ns.min
RD tac2(RD-DB)
(1.5 x tcyc-45)ns.max
DBi
Hi-Z
th(RD-DB) tsu(DB-RD)
40ns.min 0ns.min
Write timing
BCLK td(BCLK-CS)
25ns.max
th(BCLK-CS)
-3ns.min
CSi
tcyc
td(BCLK-AD)
25ns.max
th(BCLK-AD)
-3ns.min
ADi BHE td(BCLK-ALE)
25ns.max
th(BCLK-ALE)
-4ns.min
(0.5 x tcyc-10)ns.min
th(WR-AD)
ALE td(BCLK-WR)
25ns.max
th(BCLK-WR)
0ns.min
WR, WRL, WRH td(BCLK-DB)
40ns.max Hi-Z
th(BCLK-DB)
4ns.min
DBi td(DB-WR) tcyc= 1 f(BCLK)
(0.5 x tcyc-40)ns.min
th(WR-DB)
(0.5 x tcyc-10)ns.min
Measuring conditions * VCC1=VCC2=5V * Input timing voltage : VIL=0.8V, VIH=2.0V * Output timing voltage : VOL=0.4V, VOH=2.4V
Figure 21.7
Timing Diagram (5)
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21. Electrical Characteristics
VCC1=VCC2=3V
Table 21.27
Symbol VOH HIGH Output Voltage
Electrical Characteristics (1)
Parameter
(1) Measuring Condition Standard Typ. Unit
Min.
Max. VCC VCC VCC
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOH=-1mA P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
VCC-0.5 VCC-0.5 VCC-0.5 2.5 1.6
V
VOH
VOL
IOH=-0.1mA IOH=-50A HIGH Output Voltage XCOUT HIGHPOWER With no load applied LOWPOWER With no load applied P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOL=1mA LOW P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, Output P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, Voltage P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
HIGHPOWER LOWPOWER
HIGH Output Voltage
XOUT
V V
0.5 0.5 0.5 0 0
V
VOL
LOW Output Voltage XOUT LOW Output Voltage XCOUT
HIGHPOWER LOWPOWER HIGHPOWER LOWPOWER
IOL=0.1mA IOL=50A With no load applied With no load applied
V V
VT+-VT-
Hysteresis
TA0IN to TA2IN, TB0IN to TB2IN, INT0 to INT4, NMI, ADTRG, CTS0 to CTS2, RXD0 to RXD2, CLK0 to CLK2, TA0OUT to TA2OUT, KI0 to KI3, SCL0 to SCL2, SDA0 to SDA2 RESET P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, XIN, RESET, CNVSS, BYTE P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, XIN, RESET, CNVSS, BYTE
0.2
0.8
V
VT+-VTIIH
Hysteresis HIGH Input Current
0.2 VI=3V
(0.7)
1.8
V
A
4.0
IIL
LOW Input Current
VI=0V
-4.0 A
RPULLUP Pull-Up Resistance RfXIN RfXCIN VRAM
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, VI=0V P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
50
100 3.0 25
500
k M M V
Feedback Resistance Feedback Resistance RAM Retention Voltage
XIN XCIN At stop mode 2.0
NOTES: 1. Referenced to VCC1 = VCC2 = 2.7 to 3.3V, VSS = 0V at Topr = -20 to 85C / -40 to 85C, f(XIN)=10MHz no wait unless otherwise specified.
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21. Electrical Characteristics
Table 21.28
Symbol ICC
Electrical Characteristics (2) (1)
Parameter Measuring Condition f(XIN)=10MHz No division One Time f(XIN)=10MHz, Flash No division Flash f(XIN)=10MHz, Memory No division Flash Memory f(XIN)=10MHz, Program VCC1=3.0V One Time f(XIN)=10MHz, Flash Program VCC1=3.0V Flash Memory f(XIN)=10MHz, Erase VCC1=3.0V Mask ROM f(XCIN)=32kHz Low power dissipation mode, ROM (3) One Time f(XCIN)=32kHz Flash Low power dissipation mode, RAM (3) f(XCIN)=32kHz Low power dissipation mode, Flash Memory (3) Flash Memory f(XCIN)=32kHz Low power dissipation mode, RAM (3) f(XCIN)=32kHz Low power dissipation mode, Flash Memory (3) f(XCIN)=32kHz Mask ROM One Time Flash Wait mode (2), Flash Memory Oscillation capability High f(XCIN)=32kHz Wait mode (2), Oscillation capability Low Stop mode Topr =25C Mask ROM Min. Standard Typ. Max. 8 8 8 12 12 22 25 11 13 13 Unit mA mA mA mA mA mA
A
In single-chip Power Supply Current (VCC1=VCC2=2.7V to 3.6V) mode, the output pins are open and other pins are VSS
25
A
350
A
25
A
420
A
6.0
A
1.8 0.7 3.0
A A
NOTES: 1. Referenced to VCC1=VCC2=2.7 to 3.3V, VSS = 0V at Topr = -20 to 85C / -40 to 85C, f(XIN)=10MHz unless otherwise specified. 2. With one timer operated using fC32. 3. This indicates the memory in which the program to be executed exists.
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21. Electrical Characteristics
VCC1=VCC2=3V
Timing Requirements (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = -20 to 85C / -40 to 85C unless otherwise specified) Table 21.29
Symbol tc tw(H) tw(L) tr tf
External Clock Input (XIN input)
Parameter External Clock Input Cycle Time External Clock Input HIGH Pulse Width External Clock Input LOW Pulse Width External Clock Rise Time External Clock Fall Time Standard Min. Max. (NOTE 2) (NOTE 3) (NOTE 3) (NOTE 4) (NOTE 4) Unit ns ns ns ns ns
NOTES: 1. The condition is VCC1=VCC2=2.7 to 3.0V. 2. Calculated according to the VCC1 voltage as follows:
10 -6 --------------------------------------- [ns] 20 x VCC1 - 44
3. Calculated according to the VCC1 voltage as follows:
10 --------------------------------------- x 0.4 [ns] 20 x VCC1 - 44
-6
4. Calculated according to the VCC1 voltage as follows:
- 10 x VCC1 + 45 [ns]
Table 21.30
Symbol tac1(RD-DB) tac2(RD-DB) tsu(DB-RD) tsu(RDY-BCLK) tsu(HOLD-BCLK) th(RD-DB) th(BCLK-RDY) th(BCLK-HOLD)
Memory Expansion Mode and Microprocessor Mode
Parameter Data Input Access Time (for setting with no wait) Data Input Access Time (for setting with wait) Data Input Setup Time RDY Input Setup Time HOLD Input Setup Time Data Input Hold Time RDY Input Hold Time HOLD Input Hold Time Standard Min. Max. (NOTE 1) (NOTE 2) Unit ns ns ns ns ns ns ns ns
50 40 50 0 0 0
NOTES: 1. Calculated according to the BCLK frequency as follows:
9 0.5x10 ----------------------- - 60 [ ns ] f ( BCLK )
2. Calculated according to the BCLK frequency as follows:
9 ( n - 0.5 )x10 ----------------------------------- - 60 [ ns ] f ( BCLK )
n is "2" for 1-wait setting.
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M16C/30P Group
21. Electrical Characteristics
VCC1=VCC2=3V
Timing Requirements (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = -20 to 85C / -40 to 85C unless otherwise specified) Table 21.31
Symbol tc(TA) tw(TAH) tw(TAL) TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width
Timer A Input (Counter Input in Event Counter Mode)
Parameter Standard Min. 150 60 60 Max. Unit ns ns ns
Table 21.32
Symbol tc(TA) tw(TAH) tw(TAL)
Timer A Input (Gating Input in Timer Mode)
Parameter TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Standard Min. 600 300 300 Max. Unit ns ns ns
Table 21.33
Symbol tc(TA) tw(TAH) tw(TAL)
Timer A Input (External Trigger Input in One-shot Timer Mode)
Parameter TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Standard Min. 300 150 150 Max. Unit ns ns ns
Table 21.34
Symbol tw(TAH) tw(TAL)
Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Parameter TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Standard Min. 150 150 Max. Unit ns ns
Table 21.35
Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP)
Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)
Parameter TAiOUT Input Cycle Time TAiOUT Input HIGH Pulse Width TAiOUT Input LOW Pulse Width TAiOUT Input Setup Time TAiOUT Input Hold Time Standard Min. 3000 1500 1500 600 600 Max. Unit ns ns ns ns ns
Table 21.36
Symbol tc(TA) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN)
Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Parameter TAiIN Input Cycle Time TAiOUT Input Setup Time TAiIN Input Setup Time Standard Min. 2 500 500 Max. Unit
s ns ns
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M16C/30P Group
21. Electrical Characteristics
VCC1=VCC2=3V
Timing Requirements (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = -20 to 85C / -40 to 85C unless otherwise specified) Table 21.37
Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL)
Timer B Input (Counter Input in Event Counter Mode)
Parameter TBiIN Input Cycle Time (counted on one edge) TBiIN Input HIGH Pulse Width (counted on one edge) TBiIN Input LOW Pulse Width (counted on one edge) TBiIN Input Cycle Time (counted on both edges) TBiIN Input HIGH Pulse Width (counted on both edges) TBiIN Input LOW Pulse Width (counted on both edges) Standard Min. 150 60 60 300 120 120 Max. Unit ns ns ns ns ns ns
Table 21.38
Symbol tc(TB) tw(TBH) tw(TBL)
Timer B Input (Pulse Period Measurement Mode)
Parameter TBiIN Input Cycle Time TBiIN Input HIGH Pulse Width TBiIN Input LOW Pulse Width Standard Min. 600 300 300 Max. Unit ns ns ns
Table 21.39
Symbol tc(TB) tw(TBH) tw(TBL)
Timer B Input (Pulse Width Measurement Mode)
Parameter TBiIN Input Cycle Time TBiIN Input HIGH Pulse Width TBiIN Input LOW Pulse Width Standard Min. 600 300 300 Max. Unit ns ns ns
Table 21.40
Symbol tc(AD) tw(ADL)
A/D Trigger Input
Parameter ADTRG Input Cycle Time ADTRG Input LOW Pulse Width Standard Min. 1500 200 Max. Unit ns ns
Table 21.41
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D)
Serial Interface
Parameter CLKi Input Cycle Time CLKi Input HIGH Pulse Width CLKi Input LOW Pulse Width TXDi Output Delay Time TXDi Hold Time RXDi Input Setup Time RXDi Input Hold Time Standard Min. 300 150 150 0 100 90 Max. Unit ns ns ns ns ns ns ns
160
Table 21.42
Symbol tw(INH) tw(INL)
External Interrupt INTi Input
Parameter INTi Input HIGH Pulse Width INTi Input LOW Pulse Width Standard Min. 380 380 Max. Unit ns ns
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M16C/30P Group
21. Electrical Characteristics
VCC1=VCC2=3V
Switching Characteristics (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = -20 to 85C / -40 to 85C unless otherwise specified) Table 21.43
Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) td(BCLK-HLDA)
Memory Expansion and Microprocessor Modes (for setting with no wait)
Parameter Address Output Delay Time Address Output Hold Time (in relation to BCLK) Address Output Hold Time (in relation to RD) Address Output Hold Time (in relation to WR) Chip Select Output Delay Time Chip Select Output Hold Time (in relation to BCLK) ALE Signal Output Delay Time ALE Signal Output Hold Time RD Signal Output Delay Time RD Signal Output Hold Time WR Signal Output Delay Time WR Signal Output Hold Time Data Output Delay Time (in relation to BCLK) Data Output Hold Time (in relation to BCLK) (3) Data Output Delay Time (in relation to WR) Data Output Hold Time (in relation to WR) (3) HLDA Output Delay Time Standard Min. Max. 30 0 0 (NOTE 2) 30 0 25 -4 30 0 30 0 40 4 (NOTE 1) (NOTE 2) 40 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
See Figure 21.8
NOTES: 1. Calculated according to the BCLK frequency as follows: 9 0.5x10 f(BCLK) is 12.5MHz or less. ----------------------- - 40 [ ns ] f ( BCLK ) 2. Calculated according to the BCLK frequency as follows: 9 0.5x10 ----------------------- - 10 [ ns ] f ( BCLK ) 3. This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = -CR X ln (1-VOL / VCC1) by a circuit of the right figure. For example, when VOL = 0.2VCC1, C = 30pF, R = 1k, hold time of output "L" level is t = -30pF X 1k X In(1-0.2VCC1 / VCC1) = 6.7ns.
R DBi C
P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10
30pF
Figure 21.8
Ports P0 to P10 Measurement Circuit
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Page 260 of 291
M16C/30P Group
21. Electrical Characteristics
VCC1=VCC2=3V
Switching Characteristics (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = -20 to 85C / -40 to 85C unless otherwise specified) Table 21.44 Memory Expansion and Microprocessor Modes (for 1 wait setting and external area access)
Parameter Address Output Delay Time Address Output Hold Time (in relation to BCLK) Address Output Hold Time (in relation to RD) Address Output Hold Time (in relation to WR) Chip Select Output Delay Time Chip Select Output Hold Time (in relation to BCLK) ALE Signal Output Delay Time ALE Signal Output Hold Time RD Signal Output Delay Time RD Signal Output Hold Time WR Signal Output Delay Time WR Signal Output Hold Time Data Output Delay Time (in relation to BCLK) Data Output Hold Time (in relation to BCLK) (3) Data Output Delay Time (in relation to WR) Data Output Hold Time (in relation to WR)(3) HLDA Output Delay Time Standard Min. Max. 30 0 0 (NOTE 2) 30 0 25 See Figure 21.8 -4 30 0 30 0 40 4 (NOTE 1) (NOTE 2) 40 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) td(BCLK-HLDA)
NOTES: 1. Calculated according to the BCLK frequency as follows: 9 ( n - 0.5 )x10 ----------------------------------- - 40 [ ns ] n is "1" for 1-wait setting, f(BCLK) is 12.5MHz or less. f ( BCLK ) 2. Calculated according to the BCLK frequency as follows: 9 0.5x10 ----------------------- - 10 [ ns ] f ( BCLK ) 3. This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = -CR X ln (1-VOL / VCC1) by a circuit of the right figure. For example, when VOL = 0.2VCC1, C = 30pF, R = 1k, hold time of output "L" level is t = -30pF X 1k X In(1-0.2VCC1 / VCC1) = 6.7ns.
R DBi C
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M16C/30P Group
21. Electrical Characteristics
VCC1=VCC2=3V
XIN input
tr tw(H) tf tc tw(L)
tc(TA) tw(TAH)
TAiIN input
tw(TAL)
tc(UP) tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input (Up/down input) During Event Counter Mode TAiIN input (When count on falling edge is selected) TAiIN input (When count on rising edge is selected) Two-Phase Pulse Input in Event Counter Mode TAiIN input
tsu(TAIN-TAOUT) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN) th(TIN-UP) tsu(UP-TIN)
tc(TA)
TAiOUT input
tsu(TAOUT-TAIN) tc(TB) tw(TBH)
TBiIN input
tw(TBL) tc(AD) tw(ADL)
ADTRG input
Figure 21.9
Timing Diagram (1)
Rev.1.22 Mar 29, 2007 REJ09B0179-0122
Page 262 of 291
M16C/30P Group
21. Electrical Characteristics
VCC1=VCC2=3V
tc(CK) tw(CKH)
CLKi
tw(CKL) th(C-Q)
TXDi
td(C-Q) tsu(D-C) th(C-D)
RXDi
tw(INL)
INTi input
tw(INH)
Figure 21.10
Timing Diagram (2)
Rev.1.22 Mar 29, 2007 REJ09B0179-0122
Page 263 of 291
M16C/30P Group
21. Electrical Characteristics
Memory Expansion Mode, Microprocessor Mode
(Effective for setting with wait)
VCC1=VCC2=3V
BCLK
RD (Separate bus) WR, WRL, WRH (Separate bus)
RDY input tsu(RDY-BCLK) th(BCLK-RDY)
(Common to setting with wait and setting without wait)
BCLK
tsu(HOLD-BCLK)
th(BCLK-HOLD)
HOLD input
HLDA output td(BCLK-HLDA) P0, P1, P2, P3, P4, P5_0 to P5_2 (1)
Hi-Z
td(BCLK-HLDA)
NOTES: 1. These pins are set to high-impedance regardless of the input level of the BYTE pin, PM06 bit in PM0 register. Measuring conditions : * VCC1=VCC2=3V * Input timing voltage : Determined with VIL=0.6V, VIH=2.4V * Output timing voltage : Determined with VOL=1.5V, VOH=1.5V
Figure 21.11
Timing Diagram (3)
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Page 264 of 291
M16C/30P Group
21. Electrical Characteristics
Memory Expansion Mode, Microprocessor Mode
(for setting with no wait) Read timing
VCC1=VCC2=3V
BCLK td(BCLK-CS)
30ns.max
th(BCLK-CS)
0ns.min
CSi tcyc
td(BCLK-AD)
30ns.max
th(BCLK-AD)
0ns.min
ADi BHE
td(BCLK-ALE)
30ns.max
th(BCLK-ALE)
-4ns.min
th(RD-AD)
0ns.min
ALE td(BCLK-RD)
30ns.max
th(BCLK-RD)
0ns.min
RD tac1(RD-DB)
(0.5 x tcyc-60)ns.max
DBi
Hi-Z
tsu(DB-RD)
50ns.min
th(RD-DB)
0ns.min
Write timing
BCLK td(BCLK-CS)
30ns.max
th(BCLK-CS)
0ns.min
CSi tcyc
td(BCLK-AD)
30ns.max
th(BCLK-AD)
0ns.min
ADi BHE td(BCLK-ALE)
30ns.max
th(BCLK-ALE)
-4ns.min
th(WR-AD)
(0.5 x tcyc-10)ns.min
ALE td(BCLK-WR)
30ns.max
th(BCLK-WR)
0ns.min
WR, WRL, WRH td(BCLK-DB)
40ns.max Hi-Z
th(BCLK-DB)
4ns.min
DBi td(DB-WR) tcyc= 1 f(BCLK)
(0.5 x tcyc-40)ns.min
th(WR-DB)
(0.5 x tcyc-10)ns.min
Measuring conditions * VCC1=VCC2=3V * Input timing voltage : VIL=0.6V, VIH=2.4V * Output timing voltage : VOL=1.5V, VOH=1.5V
Figure 21.12
Timing Diagram (4)
Rev.1.22 Mar 29, 2007 REJ09B0179-0122
Page 265 of 291
M16C/30P Group
21. Electrical Characteristics
Memory Expansion Mode, Microprocessor Mode
(for 1-wait setting and external area access) Read timing
BCLK td(BCLK-CS)
30ns.max
VCC1=VCC2=3V
th(BCLK-CS)
0ns.min
CSi
tcyc
td(BCLK-AD)
30ns.max
th(BCLK-AD)
0ns.min
ADi BHE td(BCLK-ALE)
30ns.max
th(BCLK-ALE)
-4ns.min
th(RD-AD)
0ns.min
ALE td(BCLK-RD)
30ns.max
th(BCLK-RD)
0ns.min
RD tac2(RD-DB)
(1.5 x tcyc-60)ns.max
DBi
Hi-Z
th(RD-DB) tsu(DB-RD)
50ns.min 0ns.min
Write timing
BCLK td(BCLK-CS)
30ns.max
th(BCLK-CS)
0ns.min
CSi
tcyc
td(BCLK-AD)
30ns.max
th(BCLK-AD)
0ns.min
ADi BHE td(BCLK-ALE)
30ns.max
th(BCLK-ALE)
-4ns.min
(0.5 x tcyc-10)ns.min
th(WR-AD)
ALE td(BCLK-WR)
30ns.max
th(BCLK-WR)
0ns.min
WR,WRL, WRH td(BCLK-DB)
40ns.max Hi-Z
th(BCLK-DB)
4ns.min
DBi td(DB-WR) tcyc= 1 f(BCLK)
(0.5 x tcyc-40)ns.min
th(WR-DB)
(0.5 x tcyc-10)ns.min
Measuring conditions * VCC1=VCC2=3V * Input timing voltage : VIL=0.6V, VIH=2.4V * Output timing voltage : VOL=1.5V, VOH=1.5V
Figure 21.13
Timing Diagram (5)
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Page 266 of 291
M16C/30P Group
22. Usage Precaution
22. Usage Precaution
22.1 SFR 22.1.1 Register Settings
Table 22.1 Registers with Write-only Bits which can only be written to. Set these registers with immediate values. When establishing the next value by altering the present value, write the present value to the RAM as well as to the register. Transfer the next value to the register after making changes in the RAM. Table 22.1 Registers with Write-only Bits
Register Watchdog timer start register UART0 bit rateregister UART1 bit rateregister UART2 bit rate register UART0 Transmit buffer register UART1 Transmit buffer register UART2 Transmit buffer register Ups and downs flag Timer 0 register Timer 1 register Timer 2 register
Symbol WDC U0BRG U1BRG U2BRG U0TB U1TB U2TB UDF TA0 TA1 TA2
Address 000E 03A1 03A9 0379 03A3 to 03A2 03AB to 03AA 037B to 037A 0384 0387 to 0386 0389 to 0388 038B to 038A
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22.2 Reset
When supplying power to the microcomputer, the power supply voltage applied to the VCC1 and VCC2 pins must meet the conditions of SVCC.
Symbol SVCC
Parameter Power supply rising gradient (VCC1)
Min. 0.05
Standard Unit Typ. Max. V/ms
SVCC Power supply rising gradient (VCC1)
V
SVCC
0V
Figure 22.1 Timing of SVCC
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22.3 Bus
* The ROMless version can operate only in the microprocessor mode, connect the CNVSS pin to VCC1. * When resetting CNVSS pin with "H" input, contents of internal ROM cannot be read out.
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22.4 Precautions for Power Control
* When exiting stop mode by hardware reset, set RESET pin to "L" until a main clock oscillation is stabilized. * Set the MR0 bit in the TAiMR register (i=0 to 2) to "0" (pulse is not output) to use the timer A to exit stop
mode.
* When entering wait mode, insert a JMP.B instruction before a WAIT instruction. Do not execute any
instructions which can generate a write to RAM between the JMP.B and WAIT instructions. Disable the DMA transfers, if a DMA transfer may occur between the JMP.B and WAIT instructions. After the WAIT instruction, insert at least 4 NOP instructions. When entering wait mode, the instruction queue roadstead the instructions following WAIT, and depending on timing, some of these may execute before the microcomputer enters wait mode. Program example when entering wait mode Program Example: L1: FSET I ; WAIT ; Enter wait mode NOP ; More than 4 NOP instructions NOP NOP NOP * When entering stop mode, insert a JMP.B instruction immediately after executing an instruction which sets the CM10 bit in the CM1 register to Ag1Ah, and then insert at least 4 NOP instructions. When entering stop mode, the instruction queue reads ahead the instructions following the instruction which sets the CM10 bit to "1" (all clock stops), and, some of these may execute before the microcomputer enters stop mode or before the interrupt routine for returning from stop mode. Program example when entering stop mode Program Example: FSET BSET JMP.B L2: NOP NOP NOP NOP ; More than 4 NOP instructions I CM10 L2 JMP.B L1 ; Insert JMP.B instruction before WAIT instruction
; Enter stop mode ; Insert JMP.B instruction
* Wait the main clock oscillation stabilizes, before switching the clock source for CPU clock to the main clock. * Similarly, wait until the sub clock oscillates stably before switching the clock source for CPU clock to the sub
clock.
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* Suggestions to reduce power consumption
Ports The processor retains the state of each I/O port even when it goes to wait mode or to stop mode. A current flows in active I/O ports. A pass current flows in input ports that high-impedance state. When entering wait mode or stop mode, set non-used ports to input and stabilize the potential. A/D converter When A/D conversion is not performed, set the VCUT bit of ADiCON1 register to "0" (no VREF connection). When A/D conversion is performed, start the A/D conversion at least 1 s or longer after setting the VCUT bit to "1" (VREF connection). Stopping peripheral functions Use the CM0 register CM02 bit to stop the unnecessary peripheral functions during wait mode. However, because the peripheral function clock (fC32) generated from the sub-clock does not stop, this measure is not conducive to reducing the power consumption of the chip. If low speed mode or low power dissipation mode is to be changed to wait mode, set the CM02 bit to "0" (do not peripheral function clock stopped when in wait mode), before changing wait mode. Switching the oscillation-driving capacity Set the driving capacity to "LOW" when oscillation is stable.
22.5 Precautions for Protect
Set the PRC2 bit to "1" (write enabled) and then write to any address, and the PRC2 bit will be cleared to "0" (write protected). The registers protected by the PRC2 bit should be changed in the next instruction after setting the PRC2 bit to "1". Make sure no interrupts or DMA transfers will occur between the instruction in which the PRC2 bit is set to "1" and the next instruction.
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22.6 Precautions for Interrupt 22.6.1 Reading address 00000h
Do not read the address 00000h in a program. When a maskable interrupt request is accepted, the CPU reads interrupt information (interrupt number and interrupt request priority level) from the address 00000h during the interrupt sequence. At this time, the IR bit for the accepted interrupt is cleared to "0". If the address 00000h is read in a program, the IR bit for the interrupt which has the highest priority among the enabled interrupts is cleared to "0". This factors a problem that the interrupt is canceled, or an unexpected interrupt request is generated.
22.6.2
Setting the SP
Set any value in the SP(USP, ISP) before accepting an interrupt. The SP(USP, ISP) is cleared to "0000h" after reset. Therefore, if an interrupt is accepted before setting any value in the SP(USP, ISP), the program may go out of control. Especially when using NMI interrupt, set a value in the ISP at the beginning of the program. For the first and only the first instruction after reset, all interrupts including NMI interrupt are disabled.
22.6.3
The NMI Interrupt
The NMI interrupt cannot be disabled. If this interrupt is unused, connect the NMI pin to VCC1 via a resistor (pull-up). The input level of the NMI pin can be read by accessing the P8_5 bit in the P8 register. Note that the P8_5 bit can only be read when determining the pin level in NMI interrupt routine. Stop mode cannot be entered into while input on the NMI pin is low. This is because while input on the NMI pin is low the CM10 bit in the CM1 register is fixed to "0". Do not go to wait mode while input on the NMI pin is low. This is because when input on the NMI pin goes low, the CPU stops but CPU clock remains active; therefore, the current consumption in the chip does not drop. In this case, normal condition is restored by an interrupt generated thereafter. The low and high level durations of the input signal to the NMI pin must each be 2 CPU clock cycles + 300 ns or more.
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22.6.4
Changing the Interrupt Generate Factor
If the interrupt generate factor is changed, the IR bit in the interrupt control register for the changed interrupt may inadvertently be set to "1" (interrupt requested). If you changed the interrupt generate factor for an interrupt that needs to be used, be sure to clear the IR bit for that interrupt to "0" (interrupt not requested). Changing the interrupt generate factor refered to here means any act of changing the source, polarity or timing of the interrupt assigned to each software interrupt number. Therefore, if a mode change of any peripheral function involves changing the generate factor, polarity or timing of an interrupt, be sure to clear the IR bit for that interrupt to "0" (interrupt not requested) after making such changes. Refer to the description of each peripheral function for details about the interrupts from peripheral functions. Figure 22.2 shows the Procedure for Changing the Interrupt Generate Factor.
Changing the interrupt source
Disable interrupts (2, 3)
Change the interrupt generate factor (including a mode change of peripheral function)
Use the MOV instruction to clear the IR bit to "0" (interrupt not requested) (3)
Enable interrupts (2, 3)
End of change
IR bit: A bit in the interrupt control register for the interrupt whose interrupt generate factor is to be changed NOTES : 1. The above settings must be executed individually. Do not execute two or more settings simultaneously (using one instruction). 2. Use the I flag for the INTi interrupt (i = 0 to 4). For the interrupts from peripheral functions other than the INTi interrupt, turn off the peripheral function that is the source of the interrupt in order not to generate an interrupt request before changing the interrupt generate factor. In this case, if the maskable interrupts can all be disabled without causing a problem, use the I flag. Otherwise, use the corresponding ILVL2 to ILVL0 bit for the interrupt whose interrupt generate factor is to be changed. 3. Refer to 20.5.6 Rewrite the Interrupt Control Register for details about the instructions to use and the notes to be taken for instruction execution.
Figure 22.2
Procedure for Changing the Interrupt Generate Factor
22.6.5
INT Interrupt
* Either an "L" level of at least tW(INH) or an "H" level of at least tW(INL) width is necessary for the signal
input to pins INT0 through INT4 regardless of the CPU operation clock.
* If the POL bit in the INT0IC to INT4IC registers or the IFSR7 to IFSR0 bits in the IFSR register are
changed, the IR bit may inadvertently set to 1 (interrupt requested). Be sure to clear the IR bit to 0 interrupt not requested) after changing any of those register bits.
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22.6.6
Rewrite the Interrupt Control Register
(a) The interrupt control register for any interrupt should be modified in places where no requests for that interrupt may occur. Otherwise, disable the interrupt before rewriting the interrupt control register. (b) To rewrite the interrupt control register for any interrupt after disabling that interrupt, be careful with the instruction to be used. * Changing any bit other than the IR bit If while executing an instruction, a request for an interrupt controlled by the register being modified occurs, the IR bit in the register may not be set to "1" (interrupt requested), with the result that the interrupt request is ignored. If such a situation presents a problem, use the instructions shown below to modify the register. Usable instructions: AND, OR, BCLR, BSET
* Changing the IR bit
Depending on the instruction used, the IR bit may not always be cleared to "0" (interrupt not requested). Therefore, be sure to use the MOV instruction to clear the IR bit. (c) When using the I flag to disable an interrupt, refer to the sample program fragments shown below as you set the I flag. (Refer to (b) for details about rewrite the interrupt control registers in the sample program fragments.) Examples 1 through 3 show how to prevent the I flag from being set to "1" (interrupts enabled) before the interrupt control register is rewrited, owing to the effects of the internal bus and the instruction queue buffer. Example 1:Using the NOP instruction to keep the program waiting until the interrupt control register is modified INT_SWITCH1: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Set the TA0IC register to "00h". NOP ; NOP FSET I ; Enable interrupts.
The number of NOP instruction is as follows. When using HOLD function : 4.
Example 2:Using the dummy read to keep the FSET instruction waiting INT_SWITCH2: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Set the TA0IC register to "00h". MOV.W MEM, R0 ; Dummy read. FSET I ; Enable interrupts. Example 3:Using the POPC instruction to changing the I flag INT_SWITCH3: PUSHC FLG FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Set the TA0IC register to "00h". POPC FLG ; Enable interrupts.
22.6.7
Watchdog Timer Interrupt
Initialize the watchdog timer after the watchdog timer interrupt occurs.
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22.7 Precautions for DMAC 22.7.1 Write to DMAE Bit in DMiCON Register
When both of the conditions below are met, follow the steps below. Conditions * The DMAE bit is set to "1" again while it remains set (DMAi is in an active state). * A DMA request may occur simultaneously when the DMAE bit is being written. Steps (1) Write "1" to the DMAE bit and DMAS bit in the DMiCON register simultaneously(1). (2) Make sure that the DMAi is in an initial state(2) in a program. If the DMAi is not in an initial state, the above steps should be repeated.
NOTES: 1.The DMAS bit remains unchanged even if "1" is written. However, if "0" is written to this bit, it is set to "0" (DMA not requested). In order to prevent the DMAS bit from being modified to "0", "1" should be written to the DMAS bit when "1" is written to the DMAE bit. In this way the state of the DMAS bit immediately before being written can be maintained. Similarly, when writing to the DMAE bit with a read-modify-write instruction, "1" should be written to the DMAS bit in order to maintain a DMA request which is generated during execution. 2.Read the TCRi register to verify whether the DMAi is in an initial state. If the read value is equal to a value which was written to the TCRi register before DMA transfer start, the DMAi is in an initial state. (If a DMA request occurs after writing to the DMAE bit, the value written to the TCRi register is "1".) If the read value is a value in the middle of transfer, the DMAi is not in an initial state.
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22.8 Precautions for Timers 22.8.1 Timer A Timer A (Timer Mode)
22.8.1.1
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 2) register and the TAi register before setting the TAiS bit in the TABSR register to "1" (count starts). Always make sure the TAiMR register is modified while the TAiS bit remains "0" (count stops) regardless whether after reset or not. While counting is in progress, the counter value can be read out at any time by reading the TAi register. However, if the counter is read at the same time it is reloaded, the value "FFFFh" is read. Also, if the counter is read before it starts counting after a value is set in the TAi register while not counting, the set value is read.
22.8.1.2
Timer A (Event Counter Mode)
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 2) register, the TAi register, the UDF register, the ONSF register TAZIE, TA0TGL and TA0TGH bits and the TRGSR register before setting the TAiS bit in the TABSR register to "1" (count starts). Always make sure the TAiMR register, the UDF register, the TAZIE, TA0TGL and TA0TGH bits in the ONSF register and the TRGSR register are modified while the TAiS bit remains "0" (count stops) regardless whether after reset or not. While counting is in progress, the counter value can be read out at any time by reading the TAi register. However, "FFFFh" can be read in underflow, while reloading, and "0000h" in overflow. When setting TAi register to a value during a counter stop, the setting value can be read before a counter starts counting. Also, if the counter is read before it starts counting after a value is set in the TAi register while not counting, the set value is read.
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22.8.1.3
Timer A (One-shot Timer Mode)
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 2) register, the TAi register, the TA0TGL and TA0TGH bits in the ONSF register and the TRGSR register before setting the TAiS bit in the TABSR register to "1" (count starts). Always make sure the TAiMR register, the TA0TGL and TA0TGH bits and the TRGSR register are modified while the TAiS bit remains "0" (count stops) regardless whether after reset or not. When setting TAiS bit to "0" (count stop), the followings occur: * A counter stops counting and a content of reload register is reloaded. * TAiOUT pin outputs "L". * After one cycle of the CPU clock, the IR bit in the TAiIC register is set to "1" (interrupt request). Output in one-shot timer mode synchronizes with a count source internally generated. When an external trigger has been selected, one-cycle delay of a count source as maximum occurs between a trigger input to TAiIN pin and output in one-shot timer mode. The IR bit is set to "1" when timer operation mode is set with any of the following procedures: * Select one-shot timer mode after reset. * Change an operation mode from timer mode to one-shot timer mode. * Change an operation mode from event counter mode to one-shot timer mode. To use the Timer Ai interrupt (the IR bit), set the IR bit to "0" after the changes listed above have been made. When a trigger occurs, while counting, a counter reloads the reload register to continue counting after generating a re-trigger and counting down once. To generate a trigger while counting, generate a second trigger between occurring the previous trigger and operating longer than one cycle of a timer count source.
22.8.1.4
Timer A (Pulse Width Modulation Mode)
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 2) register, the TAi register, the TA0TGL and TA0TGH bits in the ONSF register and the TRGSR register before setting the TAiS bit in the TABSR register to "1" (count starts). Always make sure the TAiMR register, TA0TGL and TA0TGH bits and the TRGSR register are modified while the TAiS bit remains "0" (count stops) regardless whether after reset or not. The IR bit is set to "1" when setting a timer operation mode with any of the following procedures: * Select the PWM mode after reset. * Change an operation mode from timer mode to PWM mode. * Change an operation mode from event counter mode to PWM mode. To use the Timer Ai interrupt (interrupt request bit), set the IR bit to "0" by program after the above listed changes have been made. When setting TAiS register to "0" (count stop) during PWM pulse output, the following action occurs: * Stop counting. * When TAiOUT pin is output "H", output level is set to "L" and the IR bit is set to "1". * When TAiOUT pin is output "L", both output level and the IR bit remains unchanged.
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22.8.2
Timer B Timer B (Timer Mode)
22.8.2.1
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR (i = 0 to 2) register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to "1" (count starts). Always make sure the TBiMR register is modified while the TBiS bit remains "0" (count stops) regardless whether after reset or not. A value of a counter, while counting, can be read in TBi register at any time. "FFFFh" is read while reloading. Setting value is read between setting values in TBi register at count stop and starting a counter.
22.8.2.2
Timer B (Event Counter Mode)
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR (i = 0 to 2) register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to "1" (count starts). Always make sure the TBiMR register is modified while the TBiS bit remains "0" (count stops) regardless whether after reset or not. The counter value can be read out on-the-fly at any time by reading the TBi register. However, if this register is read at the same time the counter is reloaded, the read value is always "FFFFh". If the TBi register is read after setting a value in it while not counting but before the counter starts counting, the read value is the one that has been set in the register.
22.8.2.3
Timer B (Pulse Period/pulse Width Measurement Mode)
The timer remains idle after reset. Set the mode, count source, etc. using the TBiMR (i = 0 to 2) register before setting the TBiS bit in the TABSR or the TBSR register to "1" (count starts). Always make sure the TBiMR register is modified while the TBiS bit remains "0" (count stops) regardless whether after reset or not. To clear the MR3 bit to "0" by writing to the TBiMR register while the TBiS bit = 1 (count starts), be sure to write the same value as previously written to the TM0D0, TM0D1, MR0, MR1, TCK0 and TCK1 bits and a 0 to the MR2 bit. The IR bit in the TBiIC register (i=0 to 2) goes to "1" (interrupt request), when an effective edge of a measurement pulse is input or Timer Bi is overflowed. The factor of interrupt request can be determined by use of the MR3 bit in the TBiMR register within the interrupt routine. If the source of interrupt cannot be identified by the MR3 bit such as when the measurement pulse input and a timer overflow occur at the same time, use another timer to count the number of times Timer B has overflowed. To set the MR3 bit to "0" (no overflow), set TBiMR register with setting the TBiS bit to "1" and counting the next count source after setting the MR3 bit to "1" (overflow). Use the IR bit to detect only overflows. Use the MR3 bit only to determine the interrupt factor. When a count is started and the first effective edge is input, an indeterminate value is transferred to the reload register. At this time, Timer Bi interrupt request is not generated. A value of the counter is indeterminate at the beginning of a count. MR3 may be set to "1" and Timer Bi interrupt request may be generated between a count start and an effective edge input. For pulse width measurement, pulse widths are successively measured. Use program to check whether the measurement result is an "H" level width or an "L" level width.
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22.9 Precautions for Serial interface 22.9.1 Clock Synchronous Serial I/O Transmission/reception
22.9.1.1
With an external clock selected, and choosing the RTS function, the output level of the RTSi pin goes to "L" when the data-receivable status becomes ready, which informs the transmission side that the reception has become ready. The output level of the RTSi pin goes to "H" when reception starts. So if the RTSi pin is connected to the CTSi pin on the transmission side, the circuit can transmission and reception data with consistent timing. With the internal clock, the RTS function has no effect.
22.9.1.2
Transmission
When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0 register = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the external clock is in the high state; if the CKPOL bit in the UiC0 register = 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state. * The TE bit in the UiC1 register= 1 (transmission enabled) * The TI bit in the UiC1 register = 0 (data present in UiTB register) * If CTS function is selected, input on the CTSi pin = L
22.9.1.3
Reception
In operating the clock-synchronous serial I/O, operating a transmitter generates a shift clock. Fix settings for transmission even when using the device only for reception. Dummy data is output to the outside from the TXDi pin when receiving data. When an internal clock is selected, set the TE bit in the UiC1 register (i = 0 to 2) to 1 (transmission enabled) and write dummy data to the UiTB register, and the shift clock will thereby be generated. When an external clock is selected, set the TE bit to 1 and write dummy data to the UiTB register, and the shift clock will be generated when the external clock is fed to the CLKi input pin. When successively receiving data, if all bits of the next receive data are prepared in the UARTi receive register while the RE bit in the UiC1 register (i = 0 to 2) = 1 (data present in the UiRB register), an overrun error occurs and the OER bit in the UiRB register is set to "1" (overrun error occurred). In this case, because the content of the UiRB register is indeterminate, a corrective measure must be taken by programs on the transmit and receive sides so that the valid data before the overrun error occurred will be retransmitted. Note that when an overrun error occurred, the IR bit in the SiRIC register does not change state. To receive data in succession, set dummy data in the lower-order byte of the UiTB register every time reception is made. When an external clock is selected, the conditions must be met while if the CKPOL bit = 0, the external clock is in the high state; if the CKPOL bit = 1, the external clock is in the low state. * The RE bit in the UiC1 register= 1 (reception enabled) * The TE bit in the UiC1 register= 1 (transmission enabled) * The TI bit in the UiC1 register= 0 (data present in the UiTB register)
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22.9.2
UART Special Mode 1(I2C Mode)
22.9.2.1
When generating start, stop and restart conditions, set the STSPSEL bit in the UiSMR4 register to "0" and wait for more than half cycle of the transfer clock before setting each condition generate bit (STAREQ, RSTAREQ and STPREQ) from "0" to "1".
22.9.2.2
Special Mode 4 (SIM Mode)
A transmit interrupt request is generated by setting the U2C1 register U2IRS bit to "1" (transmission complete) and U2ERE bit to "1" (error signal output) after reset. Therefore, when using SIM mode, be sure to clear the IR bit to "0" (no interrupt request) after setting these bits.
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22.10
A/D Converter
Set ADCON0 (except bit 6), ADCON1 and ADCON2 registers when A/D conversion is stopped (before a trigger occurs). When the VCUT bit in the ADCON1 register is changed from "0" (Vref not connected) to "1" (Vref connected), start A/D conversion after passing 1 s or longer. To prevent noise-induced device malfunction or latchup, as well as to reduce conversion errors, insert capacitors between the AVCC, VREF, and analog input pins (ANi(i=0 to 7), AN0_i) each and the AVSS pin. Similarly, insert a capacitor between the VCC1 pin and the VSS pin. Figure 22.3 is an example connection of each pin. Make sure the port direction bits for those pins that are used as analog inputs are set to "0" (input mode). Also, if the TGR bit in the ADCON0 register = 1 (external trigger), make sure the port direction bit for the ADTRG pin is set to "0" (input mode). When using key input interrupts, do not use any of the four AN4 to AN7 pins as analog inputs. (A key input interrupt request is generated when the A/D input voltage goes low.) The AD frequency must be 10MHz or less. Without sample-and-hold function, limit the AD frequency to 250kHz or more. With the sample and hold function, limit the AD frequency to 1MHz or more. When changing an A/D operation mode, select analog input pin again in the CH2 to CH0 bits in the ADCON0 register.
Microcomputer
VCC1 VCC1 C4 VSS VCC1 VCC2 ANi VSS VREF C1 AVSS C3 C2 AVCC VCC1
C5
ANi: ANi, AN0_i (i=0 to 7) NOTES : 1. C10.47F, C20.47F, C3100pF, C40.1F, C50.1F (reference) 2. Use thick and shortest possible wiring to connect capacitors.
Figure 22.3
Use of Capacitors to Reduce Noise
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If the CPU reads the ADi register (i = 0 to 7) at the same time the conversion result is stored in the ADi register after completion of A/D conversion, an incorrect value may be stored in the ADi register. This problem occurs when a divide-by-n clock derived from the main clock or a subclock is selected for CPU clock. * When operating in one-shot mode Check to see that A/D conversion is completed before reading the target ADi register. (Check the IR bit in the ADIC register to see if A/D conversion is completed.) * When operating in repeat mode Use the main clock for CPU clock directly without dividing it. If A/D conversion is forcibly terminated while in progress by setting the ADST bit in the ADCON0 register to "0" (A/D conversion halted), the conversion result of the A/D converter is indeterminate. The contents of ADi registers irrelevant to A/D conversion may also become indeterminate. If while A/D conversion is underway the ADST bit is cleared to "0" in a program, ignore the values of all ADi registers. The applied intermediate potential may cause more increase in power consumption than other analog input pins (AN0 to AN3 and AN0_0 to AN0_7), since the AN4 to AN7 are used with the KI0 to KI3.
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22.11
Precautions for Programmable I/O Ports
The input threshold voltage of pins differs between programmable input/output ports and peripheral functions. Therefore, if any pin is shared by a programmable input/output port and a peripheral function and the input level at this pin is outside the range of recommended operating conditions VIH and VIL (neither "high" nor "low"), the input level may be determined differently depending on which side-the programmable input/output port or the peripheral function-is currently selected.
22.12
Electric Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers
Flash memory version and mask ROM version may have different characteristics, operating margin, noise tolerated dose, noise width dose in electrical characteristics due to internal ROM, different layout pattern, etc. When switching to the mask ROM version, conduct equivalent tests as system evaluation tests conducted in the flush memory version.
22.13
Mask ROM
When using the masked ROM version, write nothing to internal ROM area.
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22.14
Flash Memory Version
22.14.1 Functions to Inhibit Rewriting Flash Memory Rewrite
ID codes are stored in addresses 0FFFDFh, 0FFFE3h, 0FFFEBh, 0FFFEFh, 0FFFF3h, 0FFFF7h, and 0FFFFBh. If wrong data are written to theses addresses, the flash memory cannot be read or written in standard serial I/O mode. The ROMCP address is mapped in address 0FFFFFh. If wrong data is written to this address, the flash memory cannot be read or written in parallel I/O mode. In the flash memory version of MCU, these addresses are allocated to the vector addresses (H) of fixed vectors.
22.14.2 Stop mode
When the MCU enters stop mode, execute the instruction which sets the CM10 bit to "1" (stop mode) after setting the FMR01 bit to "0" (CPU rewrite mode disabled) and disabling the DMA transfer.
22.14.3 Wait mode
When shifting to wait mode, set the FMR01 bit to "0" (CPU rewrite mode disabled) before executing the WAIT instruction.
22.14.4 Low power dissipation mode
If the CM05 bit is set to "1" (main clock stop), the following commands must not be executed. * Program * Block erase * Lock bit program * Read Lock bit Status
22.14.5 Writing command and data
Write the command code and data at even addresses.
22.14.6 Program Command
Write "xx40h" in the first bus cycle and write data to the write address in the second bus cycle, and an auto program operation (data program and verify) will start. Make sure the address value specified in the first bus cycle is the same even address as the write address specified in the second bus cycle.
22.14.7 Lock Bit Program Command
Write "77h" in the first bus cycle and write "xxD0h" to the uppermost address of a block (even address, however) in the second bus cycle, and the lock bit for the specified block is cleared to "0". Make sure then address value specified in the first bus cycle is the same uppermost block address that is specified in the second bus cycle.
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22. Usage Precaution
22.14.8 Operation speed
Before entering CPU rewrite mode (EW0 or EW1 mode), set the CM11 bit in the CM1 register to "0" (main clock), select 10 MHz or less for CPU clock using the CM06 bit in the CM0 register and CM17 to CM16 bits in the CM1 register. Also, set the PM17 bit in the PM1 register to "1" (with wait state).
22.14.9 Prohibited instructions
The following instructions cannot be used in EW0 mode because they reference data in the flash memory: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction.
22.14.10
Interrupts
EW0 Mode * To use interrupts having vectors in a relocatable vector table, the vectors must be relocated in the RAM area. * The NMI and watchdog timer interrupts are available because the FMR0 and FMR1 registers are forcibly reset when either interrupt occurs. Allocate jump addresses for individual interrupt routine to the fixed vector table. Rewrite operation is aborted when the NMI or watchdog timer interrupt occurs. Execute a rewrite program again after exiting the interrupt routine. * The address match interrupt is not available because the CPU references data in the flash memory. EW1 Mode * Do not acknowledge any interrupts having vectors in the relocatable vector table or address match interrupt during auto-program or auto-erase operation. * Do not use the watchdog timer interrupt. * The NMI interrupt is available since registers FMR0 and FMR1 are forcibly reset when the interrupt occurs. Allocate a jump address for individual interrupt routine to the fixed vector table. Rewrite operation is aborted when the NMI interrupt occurs. Execute a rewrite program again after exiting the interrupt routine.
22.14.11
How to access
To set the FMR01, FMR02, or FMR11 bit to "1", write "0" and then "1" in succession. This is necessary to ensure that no interrupts or DMA transfers will occur before writing "1" after writing "0". Also only when NMI pin is "H" level.
22.14.12
Writing in the user ROM area
EW0 Mode * If the power supply voltage drops while rewriting any block in which the rewrite control program is stored, a problem may occur that the rewrite control program is not correctly rewritten and, consequently, the flash memory becomes unable to be rewritten thereafter. In this case, standard serial I/O or parallel I/O mode should be used. EW1 Mode * Avoid rewriting any block in which the rewrite control program is stored.
22.14.13
DMA transfer
In EW1 mode, make sure that no DMA transfers will occur while the FMR00 bit in the FMR0 register = 0 (during the auto program or auto erase period).
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22. Usage Precaution
22.15
One Time Flash Version
22.15.1 Stop mode
When the MCU enters stop mode, execute the instruction which sets the CM10 bit to "1" (stop mode) after setting the FMR01 bit to "0" and disabling the DMA transfer.
22.15.2 Wait mode
When shifting to wait mode, set the FMR01 bit to "0" before executing the WAIT instruction.
22.15.3 Operation speed
Before the FMR01 bit is set to "1" , set the CM11 bit in the CM1 register to "0" (main clock), select 10 MHz or less for CPU clock using the CM06 bit in the CM0 register and CM17 to CM16 bits in the CM1 register. Also, set the PM17 bit in the PM1 register to "1" (with wait state).
22.15.4 Prohibited Instructions
The following instructions cannot be used when the FMR01 bit is set to "1" because they reference data in the flash memory: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction.
22.15.5
Interrupts
When the FMR01 bit is set to "1", * To use interrupts having vectors in relocatable vector table, the vectors must be relocated in the RAM area. * The NMI and watchdog timer interrupts are available because the FMR0 and FMR1 registers are forcibly reset when either interrupt occurs. Allocate jump addresses for individual interrupt routine to fixed vector table. When the NMI or watchdog timer interrupt occurs, wait until the interrupt routine is completed and then set the FMR01 bit to "1" in order to set the FMSTP bit in the FMR0 register to "1" again. * The address match interrupt is not available because the CPU references data in the flash memory.
22.15.6 How to access
Set the FMR01 bit to 1 immediately after setting them first to 0 while a high-level ("H") signal is applied to the NMI pin. Do not generate an interrupt or a DMA transfer between setting the FMR01 bit to 0 and setting them to 1.
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22. Usage Precaution
22.16
Precautions for Noise
Connect a bypass capacitor (approximately 0.1 F) across the VCC1 and XSS pins, and VCC2 and VSS pins using the shortest and thicker possible wiring. Figure 22.4 shows the Bypass Capacitor Connection.
Bypass Capacitor Connecting Pattern Connecting Pattern
VSS
VCC2
M16C/30P Group
VSS
VCC1
Connecting Pattern
Connecting Pattern
Bypass Capacitor
Figure 22.4
Bypass Capacitor Connection
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M16C/30P Group
Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the "Packages" section of the Renesas Technology website.
JEITA Package Code P-QFP100-14x20-0.65 RENESAS Code PRQP0100JB-A Previous Code 100P6S-A MASS[Typ.] 1.6g
HD *1 80
D 51
81
50 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
*2
HE
E
ZE
Reference Symbol
Dimension in Millimeters Min 19.8 13.8 Nom 20.0 14.0 2.8 22.5 16.5 22.8 16.8 23.1 17.1 3.05 0 0.25 0.13 0 0.1 0.3 0.15 0.2 0.4 0.2 10 0.65 0.8 0.10 0.575 0.825 0.4 0.6 0.8 Max 20.2 14.2
100
D 31 E A2 1 ZD Index mark 30 F
c
A2
HD HE A A1
A
bp A1 L e y *3 bp Detail F c
e y ZD ZE L
0.5
JEITA Package Code P-LQFP100-14x14-0.50
RENESAS Code PLQP0100KB-A
Previous Code 100P6Q-A / FP-100U / FP-100UV
MASS[Typ.] 0.6g
HD *1 D
75
51 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
76
50
bp b1 HE E
Reference Symbol
*2
Dimension in Millimeters Min 13.9 13.9 Nom 14.0 14.0 1.4 15.8 15.8 16.0 16.0 16.2 16.2 1.7 0.05 0.15 0.1 0.20 0.18 0.09 0.145 0.125 0 8 0.5 0.08 0.08 1.0 1.0 0.35 0.5 1.0 0.65 0.20 0.15 0.25 Max 14.1 14.1
c1
c
D E Terminal cross section A2 HD ZE 100 26 HE A 1 Index mark ZD F 25 A1 bp b1 c A2 A c1
c
e A1 y e *3 bp L L1 Detail F x y ZD ZE L L1 x
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Appendix 2. Difference between M16C/62P and M16C/30P
Appendix 2. Difference between M16C/62P and M16C/30P
Appendix Table 2.1
Item Minimum instruction
Execution Time Supply Voltage
Function Difference (1)(1)
M16C/62P M16C/30P
62.5ns(f(XIN)=16MHz, VCC=3.0 to 5.5V) 100ns(f(XIN)=10MHz, VCC=2.7 to 5.5V) VCC1=VCC2=3.0 to 5.5V(f(XIN)=16MHz) VCC1=VCC2=2.7 to 5.5V(f(XIN)=10MHz) Single (VCC1=VCC2) 100-pin plastic mold QFP Mask ROM Flash Memory One time Flash Memory ROMless None
I/O Power Supply Package Memory
41.7ns(f(BCLK)=24MHz, VCC1=3.0 to 5.5V) 100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V) VCC1=3.0 to 5.5V, VCC2=3.0V to VCC1 (f(BCLK)=24MHz) VCC1=VCC2=2.7 to 5.5V (f(BCLK)=10MHz) Double (VCC1, VCC2) 80-pin, 100-pin, 128-pin plastic mold QFP Mask ROM Flash Memory ROMless
Voltage Detection Circuit Built-in Vdet3, Vdet4 detect Voltage down detect interrupt Voltage down detect reset (hardware reset 2) Clock Generating Circuit PLL, XIN, XCIN, On-chip oscillator System Clock Protective Built-in Function Oscillation Stop, Built-in Re-oscillation Detection Function Power Consumption 18mA(VCC1=VCC2=5V, f(BCLK)=24MHz) 8mA(VCC1=VCC2=3V, f(BCLK)=10MHz) 1.8A(VCC1=VCC2=3V, f(XCIN)=32kHz, wait mode) Memory Area Memory area expandable (4M bytes) External Device Connect 04000h to 07FFFh (PM13=0) Area 08000h to 0FFFFh(PM10=0) 10000h to 26FFFh 28000h to 7FFFFh 80000h to CFFFFh (PM13=0) D0000h to FFFFFh (Microprocessor mode)
XIN, XCIN None (protected by protect register) None
Bus Mode
Separate bus Multiplexed bus
10mA(VCC=5V, f(XIN)=16MHz) 8mA(VCC=3V, f(XIN)=10MHz) 1.8A(VCC=3V, f(XCIN)=32kHz, wait mode) 1 M bytes fixed 04000h to 07FFFh 08000h to 0FFFFh (PM10=0) 10000h to 26FFFh 28000h to 7FFFFh 80000h to CFFFFh (PM13=0 or without the PM13 bit) D0000h to FFFFFh (Microprocessor mode) Separate bus
NOTES: 1. About the details and the characteristics, refer to Hardware Manual.
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Appendix 2. Difference between M16C/62P and M16C/30P
Appendix Table 2.2
Item
Upper Address Memory Expansion Mode and
Function Difference (2)(1)
M16C/62P M16C/30P
P4_0 to P4_3(A16 to A19) : Switchable between address bus and I/O port P3_4 to P3_7(A12 to A15) : Can not be switched 1 wait fixed Variable (0 to 1 wait) Can be set for PM0, PM1, CM0, CM1, PD9 registers
P4_0 to P4_3(A16 to A19), P3_4 to P3_7(A12 to A15) Microprocessor mode : Switchable between address bus and I/O port Variable (1 to 2 waits) Variable (0 to 3 waits)
Can be set for PM0, PM1, PM2, CM0, CM1, CM2, PLC0, INVC0, INVC1, PD9, S3C, S4C, TB2SC, PCLKR, VCR2, D4INT registers Watchdog Timer Watchdog timer interrupt or watchdog timer reset is selected Count source protective mode is available 6 (INT0 to INT5) INT Interrupt Address Match Interrupt 4 Multifunction Timer 11 channels Timer A x 5 channels, Timer B x 6 channels Timer A two-phase pulse Function Z-phase (counter reset) input signal processing Timer Functions for Built-in Three-phase Motor Control Serial Interface (UART, Clock synchronous, I2C busTM (2), IEBusTM (3))x 3 (UART0 to UART2)
Access to SFR Software Wait to External Area Protect
Watchdog timer interrupt No count source protective mode 5 (INT0 to INT4) 2 6 channels Timer A x 3 channels, Timer B x 3 channels No function Z-phase (counter reset) input None
Clock Synchronous Serial I/O (SI/O3, SI/O4) A/D Converter A/D Converter Operation Mode
2 channels
(UART, Clock synchronous, I2C busTM (2)) x 2 (UART, Clock synchronous, I2C busTM (2), IEBusTM (3)) x 1 None
A/D Converter Input Pin D/A Converter Forced erase function of Flash Memory
10 bits x 8 channels Expandable up to 26 channels One-shot mode, Repeat mode, Single sweep mode, Repeat sweep mode 0, Repeat sweep mode 1 With External Op-amp mode Select from ports P0, P2, P10 8 bits x 2 channels None
10 bits x 8 channels Expandable up to 18 channels One-shot mode, Repeat mode
Without External Op-amp mode Select from ports P0, P10 None Built-in
NOTES: 1. About the details and the characteristics, refer to Hardware Manual. 2. I2C bus is a trademark of Koninklijke Philips Electronics N. V. 3. IEBus is a trademark of NEC Electronics Corporation.
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M16C/30 Group
Index
Register Index
[A] AD0 to AD7 ........................................................................ 171 ADCON0 ......................................................... 170, 173, 176 ADCON1 ......................................................... 170, 174, 177 ADCON2 ............................................................................ 171 ADIC ..................................................................................... 66 AIER ..................................................................................... 78 [B] BCNIC .................................................................................. 66 [C] CM0 ...................................................................................... 47 CM1 ...................................................................................... 48 CPSRF ........................................................................ 98, 112 CRCD ................................................................................. 180 CRCIN ................................................................................ 180 CSR ...................................................................................... 35 [D] DAR0, DAR1 ........................................................................ 86 DM0CON .............................................................................. 85 DM0IC to DM1IC .................................................................. 66 DM0IC, DM1IC ..................................................................... 66 DM0SL ................................................................................. 83 DM1CON .............................................................................. 85 DM1SL ................................................................................. 84 [F] FMR0 ....................................................................... 203, 229 FMR1 ................................................................................. 204 [I] IFSR ..................................................................................... 75 IFSR2A ................................................................................. 75 INT0IC to INT2IC ................................................................. 67 INT0IC to INT4IC ................................................................. 67 INT3IC .................................................................................. 67 INT4IC .................................................................................. 67 [K] KUPIC .................................................................................. 66 [O] ONSF ................................................................................... 97 [T] TA0 to TA2 ............................................................................ 95 TA0IC to TA2IC ..................................................................... 66 TA0MR to TA2MR ........................... 95, 100, 102, 106, 108 TA2MR ................................................................................104 TABSR .........................................................................96, 112 TB0 to TB2 .........................................................................111 TB0IC to TB2IC .................................................................... 66 TB0MR to TB2MR ................................. 111, 113, 115, 117 TCR0, TCR1 ......................................................................... 86 TRGSR ................................................................................. 97 [U] U0BCNIC .............................................................................. 66 U0BCNIC to U1BCNIC ......................................................... 66 U0BRG to U2BRG ..............................................................124 U0C0 to U2C0 ....................................................................125 U0C1 to U2C1 ....................................................................126 U0MR to U2MR ..................................................................124 U0RB to U2RB ...................................................................123 U0SMR to U2SMR .............................................................127 U0SMR2 to U2SMR2 .........................................................128 U0SMR3 to U2SMR3 .........................................................128 U0SMR4 to U2SMR4 .........................................................129 U0TB to U2TB ....................................................................123 U1BCNIC .............................................................................. 66 UCON .................................................................................127 UDF ...................................................................................... 96 [W] WDC .............................................................................. 28, 80 WDTS ................................................................................... 80 [P] P0 to P10 ............................................................................189 PCLKR .................................................................................. 48 PCR ....................................................................................191 PD0 to PD10 .......................................................................188 PM0 ...................................................................................... 30 PM1 ...........................................................................31, 32, 8 PRCR ................................................................................... 60 PUR0 to PUR1 ...................................................................190 PUR2 ..................................................................................191 [R] RMAD0 to RMAD1 ............................................................... 78 ROMCP ..............................................................................200 [S] S0RIC to S2RIC ................................................................... 66 S0TIC to S2TIC .................................................................... 66 SAR0, SAR1 ......................................................................... 86
Rev.1.22 Mar 29, 2007 REJ09B0179-0122
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REVISION HISTORY
M16C/30P Group Hardware Manual
Rev. 0.70 0.80
Date Aug 26, 2004 Mar 18, 2005
Description Page
- - -
Summary First Edition issued development support tools -> development tools BCLK -> CPU clock Table 1.1 Performance Outline of M16C/30P Group Serial interface is revised. Figure 1.2 Type., Memory Size, and Package is partly revised. Table 1.4 Pin Detection (2) is partly revised. 5.1 Hardware Reset 1 -> 5.1 Hardware Reset 6.1 Types of Processor Modes is revised. Figure 7.1 Clock Generation Circuit is partly revised. Note 3 of Figure 7.2 CM0 Register is revised. Tittle of 7.2.1 CPU Clock and BCLK is revised. 7.4.1 Normal Operation Mode is partly revised. Table 7.4 Interrupts to Exit Wait Mode is partly revised. Figure 10.1 Watchdog Timer Block Diagram is partly revised. Figure 10.3 Typical Operation of Cold start / Warm start is revised. Figure 11.3 DM1SL Register is partly revised. Figure 12.1 Timer A Configuration is revised. Figure 12.3 Timer A Block Diagram is revised. Table 12.4 Specifications in One-shot Timer Mode is revised. Table 12.5 Specifications in PWM Mode is revised. Figure 12.14 Timer B Block Diagram is partly revised. Table 12.7 Specifications in Event Counter Mode is partly revised. Figure 12.18 TBiMR Register in Event counter Mode is partly revised. Figure 12.19 TBiMR Register in Pulse Period and Pulse Width Measurement Mode is partly revised. Figure 12.20 Operation Timing when Measuring a Pulse Period is partly revised. Figure 12.21 Operation Timing when Measuring a Pulse Width is partly revised.
2 4 8 18 21 25 26 30 31 33 57 59 63 71 73 83 85 88 92 93 95 96
108 111 112 120 124 134 141
Table 13.1 Clock Synchronous Serial I/O Mode Specifications is partly revised. Figure 13.12 Transmit and Receive Operation is partly revised. 13.1.1.1 Counter Measure for Communication Error Occurs is partly revised. 13.1.2.1 Bit Rate is partly revised. Table 13.9 Example of Rates and Settings is revised. Table 13.10 I2C Mode Specifications is partly revised. Table 13.15 Special Mode 2 Specifications is partly revised. Table 13.18 SIM Mode Specifications is partly revised. C-1
REVISION HISTORY
Rev. Date
M16C/30P Group Hardware Manual
Description
Page 146 148 149 152 155 158 167 174 175 176 182 189 191 199 200 203204
Summary Table 14.1 Performance of A/D Converter is revised. ADCON1 Register of Figure 14.2 ADCON0 to ADCON1 Registers is partly revised. ADCON2 Register of Figure 14.3 ADCON2 and AD0 to AD7 Registers is partly revised. Figure 14.5 ADCON1 Register (One-shot Mode) is partly revised. Figure 14.7 ADCON1 Register (Repeat Mode) is partly revised. Figure 14.8 Analog Input Pin and External Sensor Equivalent Circuit is partly revised. Figure 16.7 PDi Registers is partly revised. Note 2 Table 17.3 A/D Conversion Characteristics is partly revised. Symbol of Table 17.4 Power Supply Circuit Timing Characteristics is partly revised. Table 17.5 Electrical Characteristics is revised. Table 17.19 Electrical Characteristics is revised. A/D converter of 18.2 Precautions for Power Control is partly revised. Note 2 of Figure 18.2 Procedure for Changing the Interrupt Generate Factor is partly revised. 18.8 Precautions for A/D Converter is partly revised. 18.8 Precautions for A/D Converter is partly revised. Appendix 2. Difference between M16C/62P and M16C/30P is added. Table 1.1 Performance Outline of M16C/30P Group is partly revised. Table 1.2 Product List is partly revised. Figure 1.2 Type No., Memory Size, and Package is partly revised. Figure 1.3 Pin Configuration is partly revised. Figure 1.4 Pin Configuration is partly revised. Tables 1.3 to 1.4 Pin Characteristics are added. Table 1.5 Pin Description is revised. 3. Memory is partly revised. Table 4.1 SFR Information is partly revised. Table 4.5 SFR Information is partly revised Figure 5.2 Reset Sequence is revised. Table 5.1 Pin Status When RESET Pin Level is "L" is revised.
1.00
Sep 01, 2005
2 4 5 6 7-8 9 14 15 19 21 22
20-23 Change Sections in Chapter 5.
25-26 5.4 Cold Start-up / Warm Start-up Determine Function is added. 27-30 6. Processor Mode is revised. 31-39 7. Bus is Added. 40 45 8. Memory Space Expansion Function is added. Figure 9.5 Example of Main Clock Connection Circuit is partly revised.
C-2
REVISION HISTORY
Rev. Date
M16C/30P Group Hardware Manual
Description
Page 46 49 50 51 76 78 83 85 115 116 117 119 126 129 134 137 138 144 161 163 178 179
Summary Figure 9.6 Example of Sub Clock Connection Circuit is partly revised. Table 9.3 Pin Status During Wait Mode is partly revised. Table 9.4 Interrupts to Exit Wait Mode and Use Conditions is partly revised. 9.4.3 Stop Mode is partly revised. Table 9.5 Interrupts to Exit Stop Mode and Use Conditions id added. 12.1 Cold Start / Warm Start moved to 5. Reset. Table 13.1 DMAC Specifications is partly revised. 13.1.2 Effect of BYTE Pin Level is added. Table 13.2 DMA Transfer Cycles is partly revised. Table 13.3 Coefficient J, k is partly revised. Figure 15.1 UART0 Block Diagram is partly revised. Figure 15.2 UART1 Block Diagram is partly revised. Figure 15.3 UART2 Block Diagram is partly revised. Note 3 is added in Figure 15.5 UiRB Register. Note 2 is partly revised in Table 15.1 Clock Synchronous Serial I/O Mode Specifications. Figure 15.12 Transmit and Receive Operation is revised. Note 1 is partly revised in Table 15.5 UART Mode Specifications. Figure 15.18 Transmit Operation is revised. Table 15.9 Example of Bit Rates and Settings is partly revised. Note 4 is added in table 15.11 Registers to Be Used and Settings in I2C Mode. Figure 15.33 Transmit and Receive Timing in SIM Mode is revised. 15.1.6.2 Format is revised. Figure 17.3 CRC Calculation is partly revised. 18.1 Port Pi Direction Register is partly revised. 18.2 Port Pi Register is partly revised. 18.3 Pull-up Control Register 0 to Pull-up Control Register 2 is partly revised.
184 185 186 187 190 191 193 194
Figure 18.6 I/O Pins is partly revised. Note 2 is added in Figure 18.7 PDi Registers. Note 2 is added in Figure 18.8 Pi Registers. Note 2 is added in Figure 18.9 PUR0 Register. Note 3 to 5 are added in Figure 18.9 PUR1 Register. Table 18.2 Unassigned Pin Handling in Memory Expansion Mode and Microprocessor Mode is added. Figure 18.11 Unassigned Pins Handling is revised. Table 19.2 Recommended Operating Conditions is partly revised. Table 19.3 A/D Conversion Characteristics is partly revised.
C-3
REVISION HISTORY
Rev. Date
M16C/30P Group Hardware Manual
Description
Page 197 200
Summary Note 1 is added in Table 19.6 External Clock Input (XIN input) Table 19.7 Memory Expansion Mode and Microprocessor Mode is added. Table 19.20 Memory Expansion Mode and Microprocessor Modes (for setting with no wait) is added. Figure 19.2 Ports P0 to P10 Measurement Circuit is added. Table 19.21 Memory Expansion Mode and Microprocessor Modes (for 1to 3-wait setting and external area access) is added. Figure 19.5 Timing Diagram (3) is added. Figure 19.6 Timing Diagram (4) is added. Figure 19.7 Timing Diagram (5) is added. Note 1 to 4 are added in Table 19.23 External Clock Input (XIN input) Table 19.24 Memory Expansion Mode and Microprocessor Mode is added.
201 204 205 206 208
211
Table 19.37 Memory Expansion Mode and Microprocessor Modes (for setting with no wait) is added. Figure 19.8 Ports P0 to P10 Measurement Circuit is added. Table 19.38 Memory Expansion Mode and Microprocessor Modes (for 1to 3-wait setting and external area access) is added. Figure 19.11 Timing Diagram (3) is added. Figure 19.12 Timing Diagram (4) is added. Figure 19.13 Timing Diagram (5) is added. 20.2 Bus is added. 20.3 Precautions for Power Control is revised. Figure 20.3 Use of Capacitors to Reduce Noise is partly revised. 20.8 Precautions for A/D Converter is partly revised.
212 215 216 217 219 220 231 232
235-236 Appendix Table 2.1 to 2.2 are partly revised.
C-4
REVISION HISTORY
Rev. 1.10 Date Oct 01, 2005
M16C/30P Group Hardware Manual
Description
Page 2 4 5
Summary Table 1.1 Performance Outline of M16C/30P Group is partly revised. Table 1.2 Product List is partly revised. Figure 1.2 Type No., Memory Size, and Package is partly revised. Table 1.3 Product Code of Mask ROM version Version for M16C/30P is added. Figure 1.3 Marking Diagram of Mask ROM Version for M16C/30P is added.
6 6 16 32 54 85 99 101 123 194 236 1.11 May 31, 2006 1 2 4 5 7
Figure 1.4 Marking Diagram of ROM -less Version for M16C/30P is added. Table 1.4 Product Code of ROM-less version for M16C/30P is added. Figure 3.1 Memory Map is partly added. Figure 6.3 Memory Map is partly added. 9.4.3.3 Exiting Stop Mode is partly revised. 13.1 Transfer Cycles information is added. 14.1.2 Event Counter Mode is partly revised. Information is added Note 5 is added in Figure 15.7 UiC0 Register. Table 19.2 information is revised. Appendix Table 2.1 Function Difference Memory is partly added. A note is add in Chapter 1. Overview. Table 1.1 Performance Outline of M16C/30P Group is partly revised. 1.4 Product List information is added. Table 1.2 Product List is partly revised. Figure 1.2 Type No., Memory Size, and Package is added. Table 1.4 Product Code of Flash Memory version and ROM-less version for M16C/30P is added. Figure 1.4 Marking Diagram of Flash Memory version and ROM-less Version for M16C/30P (Top View) is partly added.
17 18 19 23 29 31 32 39 42 62 63 65
3. Memory information is revised. Figure 3.1 Memory Map is partly revised. Table 4.1 SFR Information(1) is partly revised. Table 4.2 SFR Information(2) is partly added. 5.1 Hardware Reset information is deleted. Table 6.1 Features of Processor Modes is partly deleted. Figure 6.2 PM1 Register is partly revised. Figure 6.3 Memory Map in Single Chip Mode is partly added.
Table 7.5 Pin Functions for Each Processor Mode NOTES is partly deleted. Figure 8.1 Memory Mapping and CS Area in 1-Mbyte mode is partly revised.
11.4.1 Fixed Vector Tables Information is added. Table 11.2 Relocatable Vector Tables is partly added. Figure 11.4 Interrupt Control Registers (2) NOTES 4 is added.
C-5
REVISION HISTORY
Rev. Date
M16C/30P Group Hardware Manual
Description
Page 73 75 77 85 89 90 98 104 106 111 115 128 136 145 147 154 156 161 180 190 191 192 193 208 211 219 220 224 225 227
Summary Figure 11.11 IFSR and IFSR2A Registers NOTES is added. 11.9 Address Match Interrupt information is added. Figure 12.1 Watchdog Timer Block Diagram is partly revised. 13.1 Transfer Cycles is entirely revised. 13.5 Channel Priority and DMA Transfer Timing is partly added. Figure 14.1 Timer A Configuration is partly deleted. Figure 14.8 TAiMR Register in Timer Mode is partly added. Figure 14.11 TAiMR Register in One-Shot Timer Mode is partly added. Figure 14.12 TAiMR Register in PWM Mode is partly added. Figure 14.18 TBiMR Register in Timer Mode is partly added. Figure 14.20 TBiMR Register in Pulse Period and Pulse Width Measurement Mode is partly added.
Table 15.1 Clock Synchronous Serial I/O Mode Specifications is partly added.
Table 15.5 UART Mode Specifications is partly added. Figure 15.24 I2C Mode Block Diagram is partly revised.
Table 15.12 Registers to Be Used and Settings in I2C Mode (2) is partly added.
Table 15.15 Special Mode 2 Specifications is partly added. Table 15.16 Registers to Be Used and Settings in Special Mode 2 is partly revised. Table 15.18 SIM Mode Specifications is partly added. 18. Programmable I/O Ports Information is revised. Table 18.1 Unassigned Pin Handling in Single-chip Mode is partly revised. Table 18.2 Unassigned Pin Handling in Memory Expansion Mode and Microprocessor Mode is partly revised. Figure 18.11 Unassigned Pins Handling is partly revised. 19. Flash Memory Version is added. Table 19.4 Software Commands NOTES: 1 is partly revised. 19.3.5.6 Erase All Unlocked Block is partly revised. Figure 19.14 Pin Connections for Serial I/O Mode (1) Figure 19.15 Pin Connections for Serial I/O Mode (2) is partly revised. Table 20.1 Absolute Maximum Ratings is partly revised. Table 20.2 Recommended Operating Conditions is partly revised. Table 20.4 Flash Memory Version Electrical Characteristic sum Ratings and Table 20.5 Flash Memory Version Program / Erase Voltage and Read Operation Voltage Characteristics is added. Table 20.7 Electrical Characteristics (1) is partly revised. Table 20.8 Electrical Characteristics (2) is partly revised. Table 20.23 Memory Expansion and Microprocessor Modes (for setting with no wait) is partly revised. Table 20.24 Memory Expansion and Microprocessor Modes (for 1 wait setting and external area access) is partly revised. C-6
229 230 234 235
REVISION HISTORY
Rev. Date
M16C/30P Group Hardware Manual
Description
Page 241 242 246 247 253 255 267 269
Summary Table 20.25 Electrical Characteristics (1) is partly revised. Table 20.26 Electrical Characteristics (2) is partly revised. Table 20.41 Memory Expansion and Microprocessor Modes (for setting with no wait) is partly revised. Table 20.42 Memory Expansion and Microprocessor Modes (for 1 wait setting and external area access) is partly revised. 21.1 SFR, 21.1.1 Register Settings, and Table 21.1 Registers with Writeonly Bits is added. 21.3 Bus information is added. Figure 21.3 Use of Capacitors to Reduce Noise is partly revised. 21.12 Electric Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers information is added.
270-272 21.14 Flash Memory Version information is added.
1.21
Jan 24, 2007 All chapters Added the contents relevant to one-time flash to body texts, tables, and diagrams to all chapters. Deleted Erase all unlock block command in all chapters. Type No. AE Part No. 2 4 17 32 33 43 Table 1.1 Performance Outline of M16C/30P Group is partly revised. Table 1.2 Product List is partly revised. Figure 3.1 Memory Map is partly revised. Figure 6.3 PM1 Register (2) (M30304GDPFP, M30304GDPGP, M30304GEPFP, M30304GEPGP, M30302GGPFP, M30302GGPGP) is partly revised. Figure 6.4 Memory Map in Single Chip Mode is partly revised. 8. Memory Space Expansion Function Figure 8.1 Memory Mapping and CS Area in 1-Mbyte mode (PM13=0) is partly revised. Figure 8.2 Memory Mapping and CS Area in 1-Mbyte mode (PM13=1) is partly revised. Table 15.1 Clock Synchronous Serial I/O Mode Specifications is partly revised. Table 15.5 UART Mode Specifications is partly revised. Table 15.10 I2C Mode Specifications is partly revised. Table 15.11 Registers to Be Used and Settings in I2C Mode (1) is partly revised. Table 15.15 Special Mode 2 Specifications is partly revised. Table 15.18 SIM Mode Specifications is partly revised. Figure 19.1 Flash Memory Block Diagram 19.2.2 ID Code Check Function, Table 19.3 Reserved Character Sequence (Reserved Word) is added. 19.2.3 Forced Erase Function, Table 19.4 Forced Erase Function is added. Chapter 20. One Time Flash Version is added. Table 21.4 Flash Memory Version Electrical Characteristics (1) is partly revised. 22.14.4 Low power dissipation mode is partly added. Appendix Table 2.1 Function Difference (1) is partly added. Appendix Table 2.2 Function Difference (2) is partly added.
44 130 138 146 148 156 163 197 199 200 229 241 285 290 291
C-7
REVISION HISTORY
Rev. 1.22 Date Mar 29, 2007
M16C/30P Group Hardware Manual
Description
Page 4 5 19 31 32
Summary Table 1.2 Product List (1) is partly revised. Table 1.3 Product List (2) is partly revised. Table 4.2 SFR Information (2) is partly revised. Figure 6.2 PM1 Register (1) is partly revised. Figure 6.3 PM1 Register (2) (M30304GDPFP, M30304GDPGP, M30304GEPFP, M30304GEPGP, M30302GGPFP, M30302GGPGP) is partly deleted. Table 19.1 Flash Memory Version Specifications is partly deleted. Table 19.2 Flash Memory Rewrite Modes Overview is partly revised. Table 19.5 EW0 Mode and EW1 Mode is partly revised. Figure 19.4 FMR0 Register is partly added. 19.3.3.4 FMSTP Bit is partly added. 20. One Time Flash Version is partly revised. Table 20.1 One Time Flash Memory Version Specifications is partly added. Table 20.2 One Time Flash Memory Rewrite Modes Overview is partly added.
195 201 203 205 228
C-8
M16C/30P Group Hardware Manual Publication Date : Rev.1.22 Mar 29, 2007
Published by : Sales Strategic Planning Div. Renesas Technology Corp.
(c) 2007. Renesas Technology Corp., All rights reserved. Printed in Japan
M16C/30P Group Hardware Manual
2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan

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